; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

declare <16 x i8> @llvm.loongarch.lsx.vmin.b(<16 x i8>, <16 x i8>)

define <16 x i8> @lsx_vmin_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
; CHECK-LABEL: lsx_vmin_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmin.b $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i8> @llvm.loongarch.lsx.vmin.b(<16 x i8> %va, <16 x i8> %vb)
  ret <16 x i8> %res
}

declare <8 x i16> @llvm.loongarch.lsx.vmin.h(<8 x i16>, <8 x i16>)

define <8 x i16> @lsx_vmin_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
; CHECK-LABEL: lsx_vmin_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmin.h $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i16> @llvm.loongarch.lsx.vmin.h(<8 x i16> %va, <8 x i16> %vb)
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vmin.w(<4 x i32>, <4 x i32>)

define <4 x i32> @lsx_vmin_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
; CHECK-LABEL: lsx_vmin_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmin.w $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vmin.w(<4 x i32> %va, <4 x i32> %vb)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vmin.d(<2 x i64>, <2 x i64>)

define <2 x i64> @lsx_vmin_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
; CHECK-LABEL: lsx_vmin_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmin.d $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vmin.d(<2 x i64> %va, <2 x i64> %vb)
  ret <2 x i64> %res
}

declare <16 x i8> @llvm.loongarch.lsx.vmini.b(<16 x i8>, i32)

define <16 x i8> @lsx_vmini_b(<16 x i8> %va) nounwind {
; CHECK-LABEL: lsx_vmini_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmini.b $vr0, $vr0, 15
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i8> @llvm.loongarch.lsx.vmini.b(<16 x i8> %va, i32 15)
  ret <16 x i8> %res
}

declare <8 x i16> @llvm.loongarch.lsx.vmini.h(<8 x i16>, i32)

define <8 x i16> @lsx_vmini_h(<8 x i16> %va) nounwind {
; CHECK-LABEL: lsx_vmini_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmini.h $vr0, $vr0, 15
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i16> @llvm.loongarch.lsx.vmini.h(<8 x i16> %va, i32 15)
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vmini.w(<4 x i32>, i32)

define <4 x i32> @lsx_vmini_w(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vmini_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmini.w $vr0, $vr0, -16
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vmini.w(<4 x i32> %va, i32 -16)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vmini.d(<2 x i64>, i32)

define <2 x i64> @lsx_vmini_d(<2 x i64> %va) nounwind {
; CHECK-LABEL: lsx_vmini_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmini.d $vr0, $vr0, -16
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vmini.d(<2 x i64> %va, i32 -16)
  ret <2 x i64> %res
}

declare <16 x i8> @llvm.loongarch.lsx.vmin.bu(<16 x i8>, <16 x i8>)

define <16 x i8> @lsx_vmin_bu(<16 x i8> %va, <16 x i8> %vb) nounwind {
; CHECK-LABEL: lsx_vmin_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmin.bu $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i8> @llvm.loongarch.lsx.vmin.bu(<16 x i8> %va, <16 x i8> %vb)
  ret <16 x i8> %res
}

declare <8 x i16> @llvm.loongarch.lsx.vmin.hu(<8 x i16>, <8 x i16>)

define <8 x i16> @lsx_vmin_hu(<8 x i16> %va, <8 x i16> %vb) nounwind {
; CHECK-LABEL: lsx_vmin_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmin.hu $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i16> @llvm.loongarch.lsx.vmin.hu(<8 x i16> %va, <8 x i16> %vb)
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vmin.wu(<4 x i32>, <4 x i32>)

define <4 x i32> @lsx_vmin_wu(<4 x i32> %va, <4 x i32> %vb) nounwind {
; CHECK-LABEL: lsx_vmin_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmin.wu $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vmin.wu(<4 x i32> %va, <4 x i32> %vb)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vmin.du(<2 x i64>, <2 x i64>)

define <2 x i64> @lsx_vmin_du(<2 x i64> %va, <2 x i64> %vb) nounwind {
; CHECK-LABEL: lsx_vmin_du:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmin.du $vr0, $vr0, $vr1
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vmin.du(<2 x i64> %va, <2 x i64> %vb)
  ret <2 x i64> %res
}

declare <16 x i8> @llvm.loongarch.lsx.vmini.bu(<16 x i8>, i32)

define <16 x i8> @lsx_vmini_bu(<16 x i8> %va) nounwind {
; CHECK-LABEL: lsx_vmini_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmini.bu $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i8> @llvm.loongarch.lsx.vmini.bu(<16 x i8> %va, i32 31)
  ret <16 x i8> %res
}

declare <8 x i16> @llvm.loongarch.lsx.vmini.hu(<8 x i16>, i32)

define <8 x i16> @lsx_vmini_hu(<8 x i16> %va) nounwind {
; CHECK-LABEL: lsx_vmini_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmini.hu $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i16> @llvm.loongarch.lsx.vmini.hu(<8 x i16> %va, i32 31)
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vmini.wu(<4 x i32>, i32)

define <4 x i32> @lsx_vmini_wu(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vmini_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmini.wu $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vmini.wu(<4 x i32> %va, i32 31)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vmini.du(<2 x i64>, i32)

define <2 x i64> @lsx_vmini_du(<2 x i64> %va) nounwind {
; CHECK-LABEL: lsx_vmini_du:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vmini.du $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vmini.du(<2 x i64> %va, i32 31)
  ret <2 x i64> %res
}