; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

declare <16 x i8> @llvm.loongarch.lsx.vreplvei.b(<16 x i8>, i32)

define <16 x i8> @lsx_vreplvei_b(<16 x i8> %va) nounwind {
; CHECK-LABEL: lsx_vreplvei_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vreplvei.b $vr0, $vr0, 15
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i8> @llvm.loongarch.lsx.vreplvei.b(<16 x i8> %va, i32 15)
  ret <16 x i8> %res
}

declare <8 x i16> @llvm.loongarch.lsx.vreplvei.h(<8 x i16>, i32)

define <8 x i16> @lsx_vreplvei_h(<8 x i16> %va) nounwind {
; CHECK-LABEL: lsx_vreplvei_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vreplvei.h $vr0, $vr0, 7
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i16> @llvm.loongarch.lsx.vreplvei.h(<8 x i16> %va, i32 7)
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vreplvei.w(<4 x i32>, i32)

define <4 x i32> @lsx_vreplvei_w(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vreplvei_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vreplvei.w $vr0, $vr0, 3
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vreplvei.w(<4 x i32> %va, i32 3)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vreplvei.d(<2 x i64>, i32)

define <2 x i64> @lsx_vreplvei_d(<2 x i64> %va) nounwind {
; CHECK-LABEL: lsx_vreplvei_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vreplvei.d $vr0, $vr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vreplvei.d(<2 x i64> %va, i32 1)
  ret <2 x i64> %res
}