; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

declare <16 x i8> @llvm.loongarch.lsx.vsubi.bu(<16 x i8>, i32)

define <16 x i8> @lsx_vsubi_bu(<16 x i8> %va) nounwind {
; CHECK-LABEL: lsx_vsubi_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsubi.bu $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %res = call <16 x i8> @llvm.loongarch.lsx.vsubi.bu(<16 x i8> %va, i32 31)
  ret <16 x i8> %res
}

declare <8 x i16> @llvm.loongarch.lsx.vsubi.hu(<8 x i16>, i32)

define <8 x i16> @lsx_vsubi_hu(<8 x i16> %va) nounwind {
; CHECK-LABEL: lsx_vsubi_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsubi.hu $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i16> @llvm.loongarch.lsx.vsubi.hu(<8 x i16> %va, i32 31)
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vsubi.wu(<4 x i32>, i32)

define <4 x i32> @lsx_vsubi_wu(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vsubi_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsubi.wu $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vsubi.wu(<4 x i32> %va, i32 31)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vsubi.du(<2 x i64>, i32)

define <2 x i64> @lsx_vsubi_du(<2 x i64> %va) nounwind {
; CHECK-LABEL: lsx_vsubi_du:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsubi.du $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vsubi.du(<2 x i64> %va, i32 31)
  ret <2 x i64> %res
}