# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefixes=CHECK,RV64I
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB_OR_RV64ZBKB
# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB_OR_RV64ZBKB

---
name:            rotl_i8
body:             |
  bb.1:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: rotl_i8
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC2]], [[AND]](s32)
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
    ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C2]]
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %2:_(s64) = COPY $x10
    %0:_(s8) = G_TRUNC %2(s64)
    %3:_(s64) = COPY $x11
    %1:_(s8) = G_TRUNC %3(s64)
    %4:_(s8) = G_ROTL %0, %1(s8)
    %5:_(s64) = G_ANYEXT %4(s8)
    $x10 = COPY %5(s64)
    PseudoRET implicit $x10

...
---
name:            rotl_i16
body:             |
  bb.1:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: rotl_i16
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC2]], [[AND]](s32)
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
    ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C2]]
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %2:_(s64) = COPY $x10
    %0:_(s16) = G_TRUNC %2(s64)
    %3:_(s64) = COPY $x11
    %1:_(s16) = G_TRUNC %3(s64)
    %4:_(s16) = G_ROTL %0, %1(s16)
    %5:_(s64) = G_ANYEXT %4(s16)
    $x10 = COPY %5(s64)
    PseudoRET implicit $x10

...
---
name:            rotl_i32
body:             |
  bb.1:
    liveins: $x10, $x11

    ; RV64I-LABEL: name: rotl_i32
    ; RV64I: liveins: $x10, $x11
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC1]]
    ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
    ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[AND]](s32)
    ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
    ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[AND1]](s32)
    ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]
    ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
    ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
    ; RV64I-NEXT: PseudoRET implicit $x10
    ;
    ; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotl_i32
    ; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
    ; RV64ZBB_OR_RV64ZBKB-NEXT: {{  $}}
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[TRUNC]], [[AND]](s64)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTL]](s32)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ANYEXT]](s64)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
    %2:_(s64) = COPY $x10
    %0:_(s32) = G_TRUNC %2(s64)
    %3:_(s64) = COPY $x11
    %1:_(s32) = G_TRUNC %3(s64)
    %4:_(s32) = G_ROTL %0, %1(s32)
    %5:_(s64) = G_ANYEXT %4(s32)
    $x10 = COPY %5(s64)
    PseudoRET implicit $x10

...
---
name:            rotl_i64
body:             |
  bb.1:
    liveins: $x10, $x11

    ; RV64I-LABEL: name: rotl_i64
    ; RV64I: liveins: $x10, $x11
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
    ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
    ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
    ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
    ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
    ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
    ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND1]](s64)
    ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]]
    ; RV64I-NEXT: $x10 = COPY [[OR]](s64)
    ; RV64I-NEXT: PseudoRET implicit $x10
    ;
    ; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotl_i64
    ; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
    ; RV64ZBB_OR_RV64ZBKB-NEXT: {{  $}}
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[COPY]], [[COPY1]](s64)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROTL]](s64)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
    %0:_(s64) = COPY $x10
    %1:_(s64) = COPY $x11
    %2:_(s64) = G_ROTL %0, %1(s64)
    $x10 = COPY %2(s64)
    PseudoRET implicit $x10

...
---
name:            rotr_i8
body:             |
  bb.1:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: rotr_i8
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
    ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC3]], [[AND2]](s32)
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %2:_(s64) = COPY $x10
    %0:_(s8) = G_TRUNC %2(s64)
    %3:_(s64) = COPY $x11
    %1:_(s8) = G_TRUNC %3(s64)
    %4:_(s8) = G_ROTR %0, %1(s8)
    %5:_(s64) = G_ANYEXT %4(s8)
    $x10 = COPY %5(s64)
    PseudoRET implicit $x10

...
---
name:            rotr_i16
body:             |
  bb.1:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: rotr_i16
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC]]
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
    ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC3]], [[AND2]](s32)
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
    ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %2:_(s64) = COPY $x10
    %0:_(s16) = G_TRUNC %2(s64)
    %3:_(s64) = COPY $x11
    %1:_(s16) = G_TRUNC %3(s64)
    %4:_(s16) = G_ROTR %0, %1(s16)
    %5:_(s64) = G_ANYEXT %4(s16)
    $x10 = COPY %5(s64)
    PseudoRET implicit $x10

...
---
name:            rotr_i32
body:             |
  bb.1:
    liveins: $x10, $x11

    ; RV64I-LABEL: name: rotr_i32
    ; RV64I: liveins: $x10, $x11
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[TRUNC1]]
    ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
    ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[AND]](s32)
    ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
    ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[AND1]](s32)
    ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
    ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
    ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
    ; RV64I-NEXT: PseudoRET implicit $x10
    ;
    ; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotr_i32
    ; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
    ; RV64ZBB_OR_RV64ZBKB-NEXT: {{  $}}
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[TRUNC]], [[AND]](s64)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTR]](s32)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ANYEXT]](s64)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
    %2:_(s64) = COPY $x10
    %0:_(s32) = G_TRUNC %2(s64)
    %3:_(s64) = COPY $x11
    %1:_(s32) = G_TRUNC %3(s64)
    %4:_(s32) = G_ROTR %0, %1(s32)
    %5:_(s64) = G_ANYEXT %4(s32)
    $x10 = COPY %5(s64)
    PseudoRET implicit $x10

...
---
name:            rotr_i64
body:             |
  bb.1:
    liveins: $x10, $x11

    ; RV64I-LABEL: name: rotr_i64
    ; RV64I: liveins: $x10, $x11
    ; RV64I-NEXT: {{  $}}
    ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
    ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
    ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
    ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
    ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s64)
    ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
    ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64)
    ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]]
    ; RV64I-NEXT: $x10 = COPY [[OR]](s64)
    ; RV64I-NEXT: PseudoRET implicit $x10
    ;
    ; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotr_i64
    ; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
    ; RV64ZBB_OR_RV64ZBKB-NEXT: {{  $}}
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
    ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[COPY]], [[COPY1]](s64)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROTR]](s64)
    ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
    %0:_(s64) = COPY $x10
    %1:_(s64) = COPY $x11
    %2:_(s64) = G_ROTR %0, %1(s64)
    $x10 = COPY %2(s64)
    PseudoRET implicit $x10

...