; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s ; fold (and (or x, C), D) -> D if (C & D) == D define @and_or_nxv4i32( %A) { ; CHECK-LABEL: and_or_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv.v.i v8, 8 ; CHECK-NEXT: ret %ins1 = insertelement poison, i32 255, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer %ins2 = insertelement poison, i32 8, i32 0 %splat2 = shufflevector %ins2, poison, zeroinitializer %v1 = or %A, %splat1 %v2 = and %v1, %splat2 ret %v2 } ; (or (and X, c1), c2) -> (and (or X, c2), c1|c2) iff (c1 & c2) != 0 define @or_and_nxv2i64( %a0) { ; CHECK-LABEL: or_and_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 3 ; CHECK-NEXT: vand.vi v8, v8, 7 ; CHECK-NEXT: ret %ins1 = insertelement poison, i64 7, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer %ins2 = insertelement poison, i64 3, i32 0 %splat2 = shufflevector %ins2, poison, zeroinitializer %v1 = and %a0, %splat1 %v2 = or %v1, %splat2 ret %v2 } ; If all masked bits are going to be set, that's a constant fold. define @or_and_nxv2i64_fold( %a0) { ; CHECK-LABEL: or_and_nxv2i64_fold: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv.v.i v8, 3 ; CHECK-NEXT: ret %ins1 = insertelement poison, i64 1, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer %ins2 = insertelement poison, i64 3, i32 0 %splat2 = shufflevector %ins2, poison, zeroinitializer %v1 = and %a0, %splat1 %v2 = or %v1, %splat2 ret %v2 } ; fold (shl (shl x, c1), c2) -> (shl x, (add c1, c2)) define @combine_vec_shl_shl( %x) { ; CHECK-LABEL: combine_vec_shl_shl: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %ins1 = insertelement poison, i32 2, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer %ins2 = insertelement poison, i32 4, i32 0 %splat2 = shufflevector %ins2, poison, zeroinitializer %v1 = shl %x, %splat1 %v2 = shl %v1, %splat2 ret %v2 } ; fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) define @combine_vec_ashr_ashr( %x) { ; CHECK-LABEL: combine_vec_ashr_ashr: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %ins1 = insertelement poison, i32 2, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer %ins2 = insertelement poison, i32 4, i32 0 %splat2 = shufflevector %ins2, poison, zeroinitializer %v1 = ashr %x, %splat1 %v2 = ashr %v1, %splat2 ret %v2 } ; fold (srl (srl x, c1), c2) -> (srl x, (add c1, c2)) define @combine_vec_lshr_lshr( %x) { ; CHECK-LABEL: combine_vec_lshr_lshr: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret %ins1 = insertelement poison, i16 2, i32 0 %splat1 = shufflevector %ins1, poison, zeroinitializer %ins2 = insertelement poison, i16 4, i32 0 %splat2 = shufflevector %ins2, poison, zeroinitializer %v1 = lshr %x, %splat2 %v2 = lshr %v1, %splat2 ret %v2 } ; fold (fmul x, 1.0) -> x define @combine_fmul_one( %x) { ; CHECK-LABEL: combine_fmul_one: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %ins = insertelement poison, float 1.0, i32 0 %splat = shufflevector %ins, poison, zeroinitializer %v = fmul %x, %splat ret %v } ; fold (fmul 1.0, x) -> x define @combine_fmul_one_commuted( %x) { ; CHECK-LABEL: combine_fmul_one_commuted: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %ins = insertelement poison, float 1.0, i32 0 %splat = shufflevector %ins, poison, zeroinitializer %v = fmul %splat, %x ret %v }