; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB ; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB define @ctpop_nxv1i8( %va) { ; CHECK-LABEL: ctpop_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: vand.vx v9, v9, a0 ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: vand.vx v9, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv1i8: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv1i8( %va) ret %a } declare @llvm.ctpop.nxv1i8() define @ctpop_nxv2i8( %va) { ; CHECK-LABEL: ctpop_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: vand.vx v9, v9, a0 ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: vand.vx v9, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv2i8: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv2i8( %va) ret %a } declare @llvm.ctpop.nxv2i8() define @ctpop_nxv4i8( %va) { ; CHECK-LABEL: ctpop_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: vand.vx v9, v9, a0 ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: vand.vx v9, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv4i8: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv4i8( %va) ret %a } declare @llvm.ctpop.nxv4i8() define @ctpop_nxv8i8( %va) { ; CHECK-LABEL: ctpop_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: vand.vx v9, v9, a0 ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: vand.vx v9, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv8i8: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv8i8( %va) ret %a } declare @llvm.ctpop.nxv8i8() define @ctpop_nxv16i8( %va) { ; CHECK-LABEL: ctpop_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsrl.vi v10, v8, 1 ; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: vand.vx v10, v10, a0 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: vand.vx v10, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: vsrl.vi v10, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv16i8: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv16i8( %va) ret %a } declare @llvm.ctpop.nxv16i8() define @ctpop_nxv32i8( %va) { ; CHECK-LABEL: ctpop_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsrl.vi v12, v8, 1 ; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: vand.vx v12, v12, a0 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: vand.vx v12, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v12, v8 ; CHECK-NEXT: vsrl.vi v12, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv32i8: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv32i8( %va) ret %a } declare @llvm.ctpop.nxv32i8() define @ctpop_nxv64i8( %va) { ; CHECK-LABEL: ctpop_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsrl.vi v16, v8, 1 ; CHECK-NEXT: li a0, 85 ; CHECK-NEXT: vand.vx v16, v16, a0 ; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: li a0, 51 ; CHECK-NEXT: vand.vx v16, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v16, v8 ; CHECK-NEXT: vsrl.vi v16, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv64i8: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv64i8( %va) ret %a } declare @llvm.ctpop.nxv64i8() define @ctpop_nxv1i16( %va) { ; CHECK-LABEL: ctpop_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: lui a0, 5 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v9, v9, a0 ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: lui a0, 3 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v9, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: lui a0, 1 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: li a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv1i16: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv1i16( %va) ret %a } declare @llvm.ctpop.nxv1i16() define @ctpop_nxv2i16( %va) { ; CHECK-LABEL: ctpop_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: lui a0, 5 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v9, v9, a0 ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: lui a0, 3 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v9, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: lui a0, 1 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: li a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv2i16: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv2i16( %va) ret %a } declare @llvm.ctpop.nxv2i16() define @ctpop_nxv4i16( %va) { ; CHECK-LABEL: ctpop_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: lui a0, 5 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v9, v9, a0 ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: lui a0, 3 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v9, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: lui a0, 1 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: li a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv4i16: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv4i16( %va) ret %a } declare @llvm.ctpop.nxv4i16() define @ctpop_nxv8i16( %va) { ; CHECK-LABEL: ctpop_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsrl.vi v10, v8, 1 ; CHECK-NEXT: lui a0, 5 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v10, v10, a0 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: lui a0, 3 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v10, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: vsrl.vi v10, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: lui a0, 1 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: li a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv8i16: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv8i16( %va) ret %a } declare @llvm.ctpop.nxv8i16() define @ctpop_nxv16i16( %va) { ; CHECK-LABEL: ctpop_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsrl.vi v12, v8, 1 ; CHECK-NEXT: lui a0, 5 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v12, v12, a0 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: lui a0, 3 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v12, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v12, v8 ; CHECK-NEXT: vsrl.vi v12, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: lui a0, 1 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: li a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv16i16: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv16i16( %va) ret %a } declare @llvm.ctpop.nxv16i16() define @ctpop_nxv32i16( %va) { ; CHECK-LABEL: ctpop_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vsrl.vi v16, v8, 1 ; CHECK-NEXT: lui a0, 5 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v16, v16, a0 ; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: lui a0, 3 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v16, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v16, v8 ; CHECK-NEXT: vsrl.vi v16, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: lui a0, 1 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: li a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv32i16: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv32i16( %va) ret %a } declare @llvm.ctpop.nxv32i16() define @ctpop_nxv1i32( %va) { ; CHECK-LABEL: ctpop_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: lui a0, 349525 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v9, v9, a0 ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: lui a0, 209715 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v9, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: lui a0, 61681 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: lui a0, 4112 ; CHECK-NEXT: addi a0, a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv1i32: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv1i32( %va) ret %a } declare @llvm.ctpop.nxv1i32() define @ctpop_nxv2i32( %va) { ; CHECK-LABEL: ctpop_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsrl.vi v9, v8, 1 ; CHECK-NEXT: lui a0, 349525 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v9, v9, a0 ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: lui a0, 209715 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v9, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v9, v8 ; CHECK-NEXT: vsrl.vi v9, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: lui a0, 61681 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: lui a0, 4112 ; CHECK-NEXT: addi a0, a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv2i32: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv2i32( %va) ret %a } declare @llvm.ctpop.nxv2i32() define @ctpop_nxv4i32( %va) { ; CHECK-LABEL: ctpop_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsrl.vi v10, v8, 1 ; CHECK-NEXT: lui a0, 349525 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v10, v10, a0 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: lui a0, 209715 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v10, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: vsrl.vi v10, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: lui a0, 61681 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: lui a0, 4112 ; CHECK-NEXT: addi a0, a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv4i32: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv4i32( %va) ret %a } declare @llvm.ctpop.nxv4i32() define @ctpop_nxv8i32( %va) { ; CHECK-LABEL: ctpop_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsrl.vi v12, v8, 1 ; CHECK-NEXT: lui a0, 349525 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v12, v12, a0 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: lui a0, 209715 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v12, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v12, v8 ; CHECK-NEXT: vsrl.vi v12, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: lui a0, 61681 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: lui a0, 4112 ; CHECK-NEXT: addi a0, a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv8i32: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv8i32( %va) ret %a } declare @llvm.ctpop.nxv8i32() define @ctpop_nxv16i32( %va) { ; CHECK-LABEL: ctpop_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vsrl.vi v16, v8, 1 ; CHECK-NEXT: lui a0, 349525 ; CHECK-NEXT: addi a0, a0, 1365 ; CHECK-NEXT: vand.vx v16, v16, a0 ; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: lui a0, 209715 ; CHECK-NEXT: addi a0, a0, 819 ; CHECK-NEXT: vand.vx v16, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 2 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vadd.vv v8, v16, v8 ; CHECK-NEXT: vsrl.vi v16, v8, 4 ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: lui a0, 61681 ; CHECK-NEXT: addi a0, a0, -241 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: lui a0, 4112 ; CHECK-NEXT: addi a0, a0, 257 ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv16i32: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv16i32( %va) ret %a } ; We always emit vcpop.v for the scalable vector define @ctpop_nxv16i32_ult_two( %va) { ; CHECK-LABEL: ctpop_nxv16i32_ult_two: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vadd.vi v16, v8, -1 ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv16i32_ult_two: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: vmsleu.vi v0, v8, 1 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv16i32( %va) %cmp = icmp ult %a, shufflevector ( insertelement ( poison, i32 2, i64 0), poison, zeroinitializer) ret %cmp } define @ctpop_nxv16i32_ugt_one( %va) { ; CHECK-LABEL: ctpop_nxv16i32_ugt_one: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vadd.vi v16, v8, -1 ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv16i32_ugt_one: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: vmsgtu.vi v0, v8, 1 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv16i32( %va) %cmp = icmp ugt %a, shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) ret %cmp } define @ctpop_nxv16i32_eq_one( %va) { ; CHECK-LABEL: ctpop_nxv16i32_eq_one: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vadd.vi v16, v8, -1 ; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: vmsltu.vv v0, v16, v8 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv16i32_eq_one: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: vmseq.vi v0, v8, 1 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv16i32( %va) %cmp = icmp eq %a, shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) ret %cmp } define @ctpop_nxv16i32_ne_one( %va) { ; CHECK-LABEL: ctpop_nxv16i32_ne_one: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vadd.vi v16, v8, -1 ; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: vmsleu.vv v0, v8, v16 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv16i32_ne_one: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: vmsne.vi v0, v8, 1 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv16i32( %va) %cmp = icmp ne %a, shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) ret %cmp } declare @llvm.ctpop.nxv16i32() define @ctpop_nxv1i64( %va) { ; RV32-LABEL: ctpop_nxv1i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: lui a0, 349525 ; RV32-NEXT: addi a0, a0, 1365 ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; RV32-NEXT: vmv.v.x v10, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vand.vv v9, v9, v10 ; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: lui a0, 209715 ; RV32-NEXT: addi a0, a0, 819 ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vand.vv v10, v8, v9 ; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: vadd.vv v8, v10, v8 ; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: lui a0, 61681 ; RV32-NEXT: addi a0, a0, -241 ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: lui a0, 4112 ; RV32-NEXT: addi a0, a0, 257 ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; RV32-NEXT: vmv.v.x v9, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: li a0, 56 ; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ctpop_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: vsrl.vi v9, v8, 1 ; RV64-NEXT: lui a0, 349525 ; RV64-NEXT: addiw a0, a0, 1365 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v9, v9, a0 ; RV64-NEXT: vsub.vv v8, v8, v9 ; RV64-NEXT: lui a0, 209715 ; RV64-NEXT: addiw a0, a0, 819 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v9, v8, a0 ; RV64-NEXT: vsrl.vi v8, v8, 2 ; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vadd.vv v8, v9, v8 ; RV64-NEXT: vsrl.vi v9, v8, 4 ; RV64-NEXT: vadd.vv v8, v8, v9 ; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv1i64: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv1i64( %va) ret %a } declare @llvm.ctpop.nxv1i64() define @ctpop_nxv2i64( %va) { ; RV32-LABEL: ctpop_nxv2i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV32-NEXT: vsrl.vi v10, v8, 1 ; RV32-NEXT: lui a0, 349525 ; RV32-NEXT: addi a0, a0, 1365 ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vmv.v.x v12, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV32-NEXT: vand.vv v10, v10, v12 ; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: lui a0, 209715 ; RV32-NEXT: addi a0, a0, 819 ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vmv.v.x v10, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV32-NEXT: vand.vv v12, v8, v10 ; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vadd.vv v8, v12, v8 ; RV32-NEXT: vsrl.vi v10, v8, 4 ; RV32-NEXT: vadd.vv v8, v8, v10 ; RV32-NEXT: lui a0, 61681 ; RV32-NEXT: addi a0, a0, -241 ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vmv.v.x v10, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: lui a0, 4112 ; RV32-NEXT: addi a0, a0, 257 ; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vmv.v.x v10, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: li a0, 56 ; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ctpop_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV64-NEXT: vsrl.vi v10, v8, 1 ; RV64-NEXT: lui a0, 349525 ; RV64-NEXT: addiw a0, a0, 1365 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v10, v10, a0 ; RV64-NEXT: vsub.vv v8, v8, v10 ; RV64-NEXT: lui a0, 209715 ; RV64-NEXT: addiw a0, a0, 819 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v10, v8, a0 ; RV64-NEXT: vsrl.vi v8, v8, 2 ; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vadd.vv v8, v10, v8 ; RV64-NEXT: vsrl.vi v10, v8, 4 ; RV64-NEXT: vadd.vv v8, v8, v10 ; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv2i64: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv2i64( %va) ret %a } declare @llvm.ctpop.nxv2i64() define @ctpop_nxv4i64( %va) { ; RV32-LABEL: ctpop_nxv4i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32-NEXT: vsrl.vi v12, v8, 1 ; RV32-NEXT: lui a0, 349525 ; RV32-NEXT: addi a0, a0, 1365 ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; RV32-NEXT: vmv.v.x v16, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32-NEXT: vand.vv v12, v12, v16 ; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: lui a0, 209715 ; RV32-NEXT: addi a0, a0, 819 ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; RV32-NEXT: vmv.v.x v12, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32-NEXT: vand.vv v16, v8, v12 ; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vadd.vv v8, v16, v8 ; RV32-NEXT: vsrl.vi v12, v8, 4 ; RV32-NEXT: vadd.vv v8, v8, v12 ; RV32-NEXT: lui a0, 61681 ; RV32-NEXT: addi a0, a0, -241 ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; RV32-NEXT: vmv.v.x v12, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: lui a0, 4112 ; RV32-NEXT: addi a0, a0, 257 ; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; RV32-NEXT: vmv.v.x v12, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: li a0, 56 ; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ctpop_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64-NEXT: vsrl.vi v12, v8, 1 ; RV64-NEXT: lui a0, 349525 ; RV64-NEXT: addiw a0, a0, 1365 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v12, v12, a0 ; RV64-NEXT: vsub.vv v8, v8, v12 ; RV64-NEXT: lui a0, 209715 ; RV64-NEXT: addiw a0, a0, 819 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v12, v8, a0 ; RV64-NEXT: vsrl.vi v8, v8, 2 ; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vadd.vv v8, v12, v8 ; RV64-NEXT: vsrl.vi v12, v8, 4 ; RV64-NEXT: vadd.vv v8, v8, v12 ; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv4i64: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv4i64( %va) ret %a } declare @llvm.ctpop.nxv4i64() define @ctpop_nxv8i64( %va) { ; RV32-LABEL: ctpop_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: lui a0, 349525 ; RV32-NEXT: addi a0, a0, 1365 ; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; RV32-NEXT: vmv.v.x v24, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: lui a0, 209715 ; RV32-NEXT: addi a0, a0, 819 ; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; RV32-NEXT: vmv.v.x v16, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vadd.vv v8, v24, v8 ; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: lui a0, 61681 ; RV32-NEXT: addi a0, a0, -241 ; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; RV32-NEXT: vmv.v.x v16, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: lui a0, 4112 ; RV32-NEXT: addi a0, a0, 257 ; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; RV32-NEXT: vmv.v.x v16, a0 ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: li a0, 56 ; RV32-NEXT: vsrl.vx v8, v8, a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ctpop_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV64-NEXT: vsrl.vi v16, v8, 1 ; RV64-NEXT: lui a0, 349525 ; RV64-NEXT: addiw a0, a0, 1365 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v16, v16, a0 ; RV64-NEXT: vsub.vv v8, v8, v16 ; RV64-NEXT: lui a0, 209715 ; RV64-NEXT: addiw a0, a0, 819 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v16, v8, a0 ; RV64-NEXT: vsrl.vi v8, v8, 2 ; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vadd.vv v8, v16, v8 ; RV64-NEXT: vsrl.vi v16, v8, 4 ; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: lui a0, 4112 ; RV64-NEXT: addiw a0, a0, 257 ; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv8i64: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv8i64( %va) ret %a } ; We always emit vcpop.v for the scalable vector define @ctpop_nxv8i64_ult_two( %va) { ; CHECK-LABEL: ctpop_nxv8i64_ult_two: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v16, v8, -1 ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv8i64_ult_two: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: vmsleu.vi v0, v8, 1 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv8i64( %va) %cmp = icmp ult %a, shufflevector ( insertelement ( poison, i64 2, i64 0), poison, zeroinitializer) ret %cmp } define @ctpop_nxv8i64_ugt_one( %va) { ; CHECK-LABEL: ctpop_nxv8i64_ugt_one: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v16, v8, -1 ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv8i64_ugt_one: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: vmsgtu.vi v0, v8, 1 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv8i64( %va) %cmp = icmp ugt %a, shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) ret %cmp } define @ctpop_nxv8i64_eq_one( %va) { ; CHECK-LABEL: ctpop_nxv8i64_eq_one: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v16, v8, -1 ; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: vmsltu.vv v0, v16, v8 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv8i64_eq_one: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: vmseq.vi v0, v8, 1 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv8i64( %va) %cmp = icmp eq %a, shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) ret %cmp } define @ctpop_nxv8i64_ne_one( %va) { ; CHECK-LABEL: ctpop_nxv8i64_ne_one: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v16, v8, -1 ; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: vmsleu.vv v0, v8, v16 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: ctpop_nxv8i64_ne_one: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: vmsne.vi v0, v8, 1 ; CHECK-ZVBB-NEXT: ret %a = call @llvm.ctpop.nxv8i64( %va) %cmp = icmp ne %a, shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) ret %cmp } declare @llvm.ctpop.nxv8i64()