; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s define @masked_load_nxv1f16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv1f16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv1f16(*, i32, , ) define @masked_load_nxv1f32(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv1f32(* %a, i32 4, %mask, undef) ret %load } declare @llvm.masked.load.nxv1f32(*, i32, , ) define @masked_load_nxv1f64(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv1f64(* %a, i32 8, %mask, undef) ret %load } declare @llvm.masked.load.nxv1f64(*, i32, , ) define @masked_load_nxv2f16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv2f16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv2f16(*, i32, , ) define @masked_load_nxv2f32(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv2f32(* %a, i32 4, %mask, undef) ret %load } declare @llvm.masked.load.nxv2f32(*, i32, , ) define @masked_load_nxv2f64(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv2f64(* %a, i32 8, %mask, undef) ret %load } declare @llvm.masked.load.nxv2f64(*, i32, , ) define @masked_load_nxv4f16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv4f16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv4f16(*, i32, , ) define @masked_load_nxv4f32(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv4f32(* %a, i32 4, %mask, undef) ret %load } declare @llvm.masked.load.nxv4f32(*, i32, , ) define @masked_load_nxv4f64(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv4f64(* %a, i32 8, %mask, undef) ret %load } declare @llvm.masked.load.nxv4f64(*, i32, , ) define @masked_load_nxv8f16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv8f16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv8f16(*, i32, , ) define @masked_load_nxv8f32(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv8f32(* %a, i32 4, %mask, undef) ret %load } declare @llvm.masked.load.nxv8f32(*, i32, , ) define @masked_load_nxv8f64(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv8f64(* %a, i32 8, %mask, undef) ret %load } declare @llvm.masked.load.nxv8f64(*, i32, , ) define @masked_load_nxv16f16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv16f16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv16f16(*, i32, , ) define @masked_load_nxv16f32(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv16f32(* %a, i32 4, %mask, undef) ret %load } declare @llvm.masked.load.nxv16f32(*, i32, , ) define @masked_load_nxv32f16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv32f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv32f16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv32f16(*, i32, , )