; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s define @masked_load_nxv1i8(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vle8.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv1i8(* %a, i32 1, %mask, undef) ret %load } declare @llvm.masked.load.nxv1i8(*, i32, , ) define @masked_load_nxv1i16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv1i16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv1i16(*, i32, , ) define @masked_load_nxv1i32(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv1i32(* %a, i32 4, %mask, undef) ret %load } declare @llvm.masked.load.nxv1i32(*, i32, , ) define @masked_load_nxv1i64(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv1i64(* %a, i32 8, %mask, undef) ret %load } declare @llvm.masked.load.nxv1i64(*, i32, , ) define @masked_load_nxv2i8(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vle8.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv2i8(* %a, i32 1, %mask, undef) ret %load } declare @llvm.masked.load.nxv2i8(*, i32, , ) define @masked_load_nxv2i16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv2i16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv2i16(*, i32, , ) define @masked_load_nxv2i32(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv2i32(* %a, i32 4, %mask, undef) ret %load } declare @llvm.masked.load.nxv2i32(*, i32, , ) define @masked_load_nxv2i64(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv2i64(* %a, i32 8, %mask, undef) ret %load } declare @llvm.masked.load.nxv2i64(*, i32, , ) define @masked_load_nxv4i8(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vle8.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv4i8(* %a, i32 1, %mask, undef) ret %load } declare @llvm.masked.load.nxv4i8(*, i32, , ) define @masked_load_nxv4i16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv4i16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv4i16(*, i32, , ) define @masked_load_nxv4i32(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv4i32(* %a, i32 4, %mask, undef) ret %load } declare @llvm.masked.load.nxv4i32(*, i32, , ) define @masked_load_nxv4i64(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv4i64(* %a, i32 8, %mask, undef) ret %load } declare @llvm.masked.load.nxv4i64(*, i32, , ) define @masked_load_nxv8i8(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vle8.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv8i8(* %a, i32 1, %mask, undef) ret %load } declare @llvm.masked.load.nxv8i8(*, i32, , ) define @masked_load_nxv8i16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv8i16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv8i16(*, i32, , ) define @masked_load_nxv8i32(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv8i32(* %a, i32 4, %mask, undef) ret %load } declare @llvm.masked.load.nxv8i32(*, i32, , ) define @masked_load_nxv8i64(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv8i64(* %a, i32 8, %mask, undef) ret %load } declare @llvm.masked.load.nxv8i64(*, i32, , ) define @masked_load_nxv16i8(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vle8.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv16i8(* %a, i32 1, %mask, undef) ret %load } declare @llvm.masked.load.nxv16i8(*, i32, , ) define @masked_load_nxv16i16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv16i16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv16i16(*, i32, , ) define @masked_load_nxv16i32(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv16i32(* %a, i32 4, %mask, undef) ret %load } declare @llvm.masked.load.nxv16i32(*, i32, , ) define @masked_load_nxv32i8(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vle8.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv32i8(* %a, i32 1, %mask, undef) ret %load } declare @llvm.masked.load.nxv32i8(*, i32, , ) define @masked_load_nxv32i16(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vle16.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv32i16(* %a, i32 2, %mask, undef) ret %load } declare @llvm.masked.load.nxv32i16(*, i32, , ) define @masked_load_nxv64i8(* %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vle8.v v8, (a0), v0.t ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv64i8(* %a, i32 1, %mask, undef) ret %load } declare @llvm.masked.load.nxv64i8(*, i32, , ) define @masked_load_zero_mask(* %a) nounwind { ; CHECK-LABEL: masked_load_zero_mask: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv2i8(* %a, i32 1, zeroinitializer, undef) ret %load } define @masked_load_allones_mask(* %a, %maskedoff) nounwind { ; CHECK-LABEL: masked_load_allones_mask: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: ret %insert = insertelement poison, i1 1, i32 0 %mask = shufflevector %insert, poison, zeroinitializer %load = call @llvm.masked.load.nxv2i8(* %a, i32 1, %mask, %maskedoff) ret %load }