; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+m,+v \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+m,+v \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64 define @icmp_eq_vv_nxv3i8( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv3i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc } define @icmp_eq_vx_nxv3i8( %va, i8 %b) { ; CHECK-LABEL: icmp_eq_vx_nxv3i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_xv_nxv3i8( %va, i8 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv3i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %splat, %va ret %vc } define @icmp_eq_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc } define @icmp_eq_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_eq_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %splat, %va ret %vc } define @icmp_eq_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_eq_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i8 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_vi_nxv8i8_1( %va) { ; CHECK-LABEL: icmp_eq_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_iv_nxv8i8_1( %va) { ; CHECK-LABEL: icmp_eq_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %splat, %va ret %vc } define @icmp_ne_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_ne_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc } define @icmp_ne_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ne_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %va, %splat ret %vc } define @icmp_ne_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ne_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %splat, %va ret %vc } define @icmp_ne_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_ne_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %va, %splat ret %vc } define @icmp_ugt_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_ugt_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc } define @icmp_ugt_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ugt_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %va, %splat ret %vc } define @icmp_ugt_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ugt_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %splat, %va ret %vc } define @icmp_ugt_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_ugt_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %va, %splat ret %vc } define @icmp_uge_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_uge_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc } define @icmp_uge_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_uge_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_uge_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %splat, %va ret %vc } define @icmp_uge_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.i v9, -16 ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement poison, i8 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i8_1( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 14 ; CHECK-NEXT: ret %head = insertelement poison, i8 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_iv_nxv8i8_1( %va) { ; CHECK-LABEL: icmp_uge_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %splat, %va ret %vc } define @icmp_uge_vi_nxv8i8_2( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret %head = insertelement poison, i8 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i8_3( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i8 1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i8_4( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i8 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i8_5( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_5: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } ; Test that we don't optimize uge x, 0 -> ugt x, -1 define @icmp_uge_vi_nxv8i8_6( %va, iXLen %vl) { ; CHECK-LABEL: icmp_uge_vi_nxv8i8_6: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %splat = call @llvm.riscv.vmv.v.x.nxv8i8.iXLen( undef, i8 0, iXLen %vl) %vc = icmp uge %va, %splat ret %vc } define @icmp_ult_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_ult_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc } define @icmp_ult_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ult_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ult_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %splat, %va ret %vc } define @icmp_ult_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -16 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i8_1( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i8 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_iv_nxv8i8_1( %va) { ; CHECK-LABEL: icmp_ult_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i8 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %splat, %va ret %vc } define @icmp_ult_vi_nxv8i8_2( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret %head = insertelement poison, i8 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i8_3( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i8_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i8 1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i8_4( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i8_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } declare @llvm.riscv.vmv.v.x.nxv8i8.iXLen(, i8, iXLen); ; Test that we don't optimize ult x, 0 -> ule x, -1 define @icmp_ult_vi_nxv8i8_5( %va, iXLen %vl) { ; CHECK-LABEL: icmp_ult_vi_nxv8i8_5: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, zero ; CHECK-NEXT: ret %splat = call @llvm.riscv.vmv.v.x.nxv8i8.iXLen( undef, i8 0, iXLen %vl) %vc = icmp ult %va, %splat ret %vc } define @icmp_ule_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_ule_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc } define @icmp_ule_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ule_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %va, %splat ret %vc } define @icmp_ule_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_ule_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %splat, %va ret %vc } define @icmp_ule_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_ule_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %va, %splat ret %vc } define @icmp_sgt_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_sgt_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc } define @icmp_sgt_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sgt_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %va, %splat ret %vc } define @icmp_sgt_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sgt_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %splat, %va ret %vc } define @icmp_sgt_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_sgt_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %va, %splat ret %vc } define @icmp_sge_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_sge_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc } define @icmp_sge_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sge_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sge_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %splat, %va ret %vc } define @icmp_sge_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.i v9, -16 ; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement poison, i8 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_vi_nxv8i8_1( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i8 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_iv_nxv8i8_1( %va) { ; CHECK-LABEL: icmp_sge_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i8 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %splat, %va ret %vc } define @icmp_sge_vi_nxv8i8_2( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -1 ; CHECK-NEXT: ret %head = insertelement poison, i8 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_vi_nxv8i8_3( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i8_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_slt_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_slt_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc } define @icmp_slt_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_slt_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_slt_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %splat, %va ret %vc } define @icmp_slt_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -16 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_vi_nxv8i8_1( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i8 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_iv_nxv8i8_1( %va) { ; CHECK-LABEL: icmp_slt_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i8 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %splat, %va ret %vc } define @icmp_slt_vi_nxv8i8_2( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: ret %head = insertelement poison, i8 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_vi_nxv8i8_3( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i8_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_sle_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: icmp_sle_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc } define @icmp_sle_vx_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sle_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %va, %splat ret %vc } define @icmp_sle_xv_nxv8i8( %va, i8 %b) { ; CHECK-LABEL: icmp_sle_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.x v9, a0 ; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %splat, %va ret %vc } define @icmp_sle_vi_nxv8i8_0( %va) { ; CHECK-LABEL: icmp_sle_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %va, %splat ret %vc } define @icmp_eq_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc } define @icmp_eq_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_eq_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %splat, %va ret %vc } define @icmp_eq_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_eq_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i16 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_vi_nxv8i16_1( %va) { ; CHECK-LABEL: icmp_eq_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i16 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_iv_nxv8i16_1( %va) { ; CHECK-LABEL: icmp_eq_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i16 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %splat, %va ret %vc } define @icmp_ne_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: icmp_ne_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc } define @icmp_ne_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ne_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %va, %splat ret %vc } define @icmp_ne_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ne_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %splat, %va ret %vc } define @icmp_ne_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_ne_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i16 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %va, %splat ret %vc } define @icmp_ugt_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: icmp_ugt_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc } define @icmp_ugt_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ugt_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %va, %splat ret %vc } define @icmp_ugt_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ugt_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %splat, %va ret %vc } define @icmp_ugt_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_ugt_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i16 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %va, %splat ret %vc } define @icmp_uge_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: icmp_uge_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc } define @icmp_uge_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_uge_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_uge_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %splat, %va ret %vc } define @icmp_uge_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.v.i v10, -16 ; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement poison, i16 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i16_1( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 14 ; CHECK-NEXT: ret %head = insertelement poison, i16 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_iv_nxv8i16_1( %va) { ; CHECK-LABEL: icmp_uge_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %splat, %va ret %vc } define @icmp_uge_vi_nxv8i16_2( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret %head = insertelement poison, i16 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i16_3( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i16_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i16 1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i16_4( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i16_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i16 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i16_5( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i16_5: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_ult_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: icmp_ult_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc } define @icmp_ult_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ult_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ult_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %splat, %va ret %vc } define @icmp_ult_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -16 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i16_1( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i16 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_iv_nxv8i16_1( %va) { ; CHECK-LABEL: icmp_ult_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i16 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %splat, %va ret %vc } define @icmp_ult_vi_nxv8i16_2( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret %head = insertelement poison, i16 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i16_3( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i16_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i16 1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i16_4( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i16_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ule_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: icmp_ule_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc } define @icmp_ule_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ule_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %va, %splat ret %vc } define @icmp_ule_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_ule_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %splat, %va ret %vc } define @icmp_ule_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_ule_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i16 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %va, %splat ret %vc } define @icmp_sgt_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: icmp_sgt_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc } define @icmp_sgt_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sgt_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %va, %splat ret %vc } define @icmp_sgt_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sgt_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %splat, %va ret %vc } define @icmp_sgt_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_sgt_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i16 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %va, %splat ret %vc } define @icmp_sge_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: icmp_sge_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc } define @icmp_sge_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sge_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sge_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %splat, %va ret %vc } define @icmp_sge_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.v.i v10, -16 ; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement poison, i16 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_vi_nxv8i16_1( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i16 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_iv_nxv8i16_1( %va) { ; CHECK-LABEL: icmp_sge_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i16 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %splat, %va ret %vc } define @icmp_sge_vi_nxv8i16_2( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -1 ; CHECK-NEXT: ret %head = insertelement poison, i16 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_vi_nxv8i16_3( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i16_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_slt_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: icmp_slt_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc } define @icmp_slt_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_slt_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_slt_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %splat, %va ret %vc } define @icmp_slt_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -16 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_vi_nxv8i16_1( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i16 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_iv_nxv8i16_1( %va) { ; CHECK-LABEL: icmp_slt_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i16 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %splat, %va ret %vc } define @icmp_slt_vi_nxv8i16_2( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: ret %head = insertelement poison, i16 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_vi_nxv8i16_3( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i16_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_sle_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: icmp_sle_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc } define @icmp_sle_vx_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sle_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %va, %splat ret %vc } define @icmp_sle_xv_nxv8i16( %va, i16 %b) { ; CHECK-LABEL: icmp_sle_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %splat, %va ret %vc } define @icmp_sle_vi_nxv8i16_0( %va) { ; CHECK-LABEL: icmp_sle_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i16 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %va, %splat ret %vc } define @icmp_eq_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc } define @icmp_eq_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_eq_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_eq_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %splat, %va ret %vc } define @icmp_eq_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_eq_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i32 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_vi_nxv8i32_1( %va) { ; CHECK-LABEL: icmp_eq_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i32 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_iv_nxv8i32_1( %va) { ; CHECK-LABEL: icmp_eq_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i32 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %splat, %va ret %vc } define @icmp_ne_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: icmp_ne_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc } define @icmp_ne_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ne_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %va, %splat ret %vc } define @icmp_ne_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ne_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %splat, %va ret %vc } define @icmp_ne_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_ne_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i32 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %va, %splat ret %vc } define @icmp_ugt_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: icmp_ugt_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc } define @icmp_ugt_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ugt_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %va, %splat ret %vc } define @icmp_ugt_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ugt_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %splat, %va ret %vc } define @icmp_ugt_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_ugt_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i32 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %va, %splat ret %vc } define @icmp_uge_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: icmp_uge_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc } define @icmp_uge_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_uge_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_uge_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %splat, %va ret %vc } define @icmp_uge_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv.v.i v12, -16 ; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement poison, i32 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i32_1( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 14 ; CHECK-NEXT: ret %head = insertelement poison, i32 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_iv_nxv8i32_1( %va) { ; CHECK-LABEL: icmp_uge_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i32 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %splat, %va ret %vc } define @icmp_uge_vi_nxv8i32_2( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret %head = insertelement poison, i32 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i32_3( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i32_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i32 1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i32_4( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i32_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i32 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i32_5( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i32_5: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i32 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_ult_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: icmp_ult_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc } define @icmp_ult_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ult_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ult_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %splat, %va ret %vc } define @icmp_ult_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -16 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i32_1( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i32 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_iv_nxv8i32_1( %va) { ; CHECK-LABEL: icmp_ult_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i32 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %splat, %va ret %vc } define @icmp_ult_vi_nxv8i32_2( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret %head = insertelement poison, i32 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i32_3( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i32_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i32 1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i32_4( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i32_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i32 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ule_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: icmp_ule_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc } define @icmp_ule_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ule_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %va, %splat ret %vc } define @icmp_ule_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_ule_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %splat, %va ret %vc } define @icmp_ule_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_ule_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i32 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %va, %splat ret %vc } define @icmp_sgt_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: icmp_sgt_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc } define @icmp_sgt_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sgt_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %va, %splat ret %vc } define @icmp_sgt_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sgt_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %splat, %va ret %vc } define @icmp_sgt_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_sgt_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i32 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %va, %splat ret %vc } define @icmp_sge_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: icmp_sge_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc } define @icmp_sge_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sge_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sge_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %splat, %va ret %vc } define @icmp_sge_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv.v.i v12, -16 ; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement poison, i32 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_vi_nxv8i32_1( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i32 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_iv_nxv8i32_1( %va) { ; CHECK-LABEL: icmp_sge_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i32 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %splat, %va ret %vc } define @icmp_sge_vi_nxv8i32_2( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -1 ; CHECK-NEXT: ret %head = insertelement poison, i32 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_vi_nxv8i32_3( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i32_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i32 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_slt_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: icmp_slt_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc } define @icmp_slt_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_slt_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_slt_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %splat, %va ret %vc } define @icmp_slt_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -16 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_vi_nxv8i32_1( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i32 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_iv_nxv8i32_1( %va) { ; CHECK-LABEL: icmp_slt_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i32 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %splat, %va ret %vc } define @icmp_slt_vi_nxv8i32_2( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: ret %head = insertelement poison, i32 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_vi_nxv8i32_3( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i32_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i32 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_sle_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: icmp_sle_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc } define @icmp_sle_vx_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sle_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %va, %splat ret %vc } define @icmp_sle_xv_nxv8i32( %va, i32 %b) { ; CHECK-LABEL: icmp_sle_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %splat, %va ret %vc } define @icmp_sle_vi_nxv8i32_0( %va) { ; CHECK-LABEL: icmp_sle_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i32 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %va, %splat ret %vc } define @icmp_eq_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc } define @icmp_eq_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_eq_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmseq.vv v0, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_eq_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmseq.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_xv_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_eq_xv_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmseq.vv v0, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_eq_xv_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmseq.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %splat, %va ret %vc } define @icmp_eq_vi_nxv8i64_0( %va) { ; CHECK-LABEL: icmp_eq_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i64 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_vi_nxv8i64_1( %va) { ; CHECK-LABEL: icmp_eq_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i64 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %va, %splat ret %vc } define @icmp_eq_iv_nxv8i64_1( %va) { ; CHECK-LABEL: icmp_eq_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i64 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp eq %splat, %va ret %vc } define @icmp_ne_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ne_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsne.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc } define @icmp_ne_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_ne_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsne.vv v0, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_ne_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsne.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %va, %splat ret %vc } define @icmp_ne_xv_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_ne_xv_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsne.vv v0, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_ne_xv_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsne.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %splat, %va ret %vc } define @icmp_ne_vi_nxv8i64_0( %va) { ; CHECK-LABEL: icmp_ne_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i64 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ne %va, %splat ret %vc } define @icmp_ugt_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ugt_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsltu.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc } define @icmp_ugt_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_ugt_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_ugt_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsgtu.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %va, %splat ret %vc } define @icmp_ugt_xv_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_ugt_xv_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_ugt_xv_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsltu.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %splat, %va ret %vc } define @icmp_ugt_vi_nxv8i64_0( %va) { ; CHECK-LABEL: icmp_ugt_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i64 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ugt %va, %splat ret %vc } define @icmp_uge_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_uge_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc } define @icmp_uge_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_uge_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_uge_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vmsleu.vv v0, v16, v8 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_xv_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_uge_xv_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_uge_xv_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsleu.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %splat, %va ret %vc } define @icmp_uge_vi_nxv8i64_0( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv.v.i v16, -16 ; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement poison, i64 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i64_1( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 14 ; CHECK-NEXT: ret %head = insertelement poison, i64 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_iv_nxv8i64_1( %va) { ; CHECK-LABEL: icmp_uge_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i64 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %splat, %va ret %vc } define @icmp_uge_vi_nxv8i64_2( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret %head = insertelement poison, i64 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i64_3( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i64 1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i64_4( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i64_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i64 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_uge_vi_nxv8i64_5( %va) { ; CHECK-LABEL: icmp_uge_vi_nxv8i64_5: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp uge %va, %splat ret %vc } define @icmp_ult_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ult_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsltu.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc } define @icmp_ult_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_ult_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_ult_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsltu.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_xv_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_ult_xv_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_ult_xv_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsgtu.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %splat, %va ret %vc } define @icmp_ult_vi_nxv8i64_0( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -16 ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i64 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i64_1( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i64 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_iv_nxv8i64_1( %va) { ; CHECK-LABEL: icmp_ult_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i64 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %splat, %va ret %vc } define @icmp_ult_vi_nxv8i64_2( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret %head = insertelement poison, i64 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i64_3( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i64 1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ult_vi_nxv8i64_4( %va) { ; CHECK-LABEL: icmp_ult_vi_nxv8i64_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ult %va, %splat ret %vc } define @icmp_ule_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ule_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc } define @icmp_ule_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_ule_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_ule_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsleu.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %va, %splat ret %vc } define @icmp_ule_xv_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_ule_xv_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_ule_xv_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vmsleu.vv v0, v16, v8 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %splat, %va ret %vc } define @icmp_ule_vi_nxv8i64_0( %va) { ; CHECK-LABEL: icmp_ule_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i64 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp ule %va, %splat ret %vc } define @icmp_sgt_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_sgt_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmslt.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc } define @icmp_sgt_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_sgt_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmslt.vv v0, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_sgt_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsgt.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %va, %splat ret %vc } define @icmp_sgt_xv_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_sgt_xv_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmslt.vv v0, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_sgt_xv_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmslt.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %splat, %va ret %vc } define @icmp_sgt_vi_nxv8i64_0( %va) { ; CHECK-LABEL: icmp_sgt_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i64 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sgt %va, %splat ret %vc } define @icmp_sge_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_sge_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc } define @icmp_sge_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_sge_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsle.vv v0, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_sge_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vmsle.vv v0, v16, v8 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_xv_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_sge_xv_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsle.vv v0, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_sge_xv_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsle.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %splat, %va ret %vc } define @icmp_sge_vi_nxv8i64_0( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv.v.i v16, -16 ; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement poison, i64 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_vi_nxv8i64_1( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i64 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_iv_nxv8i64_1( %va) { ; CHECK-LABEL: icmp_sge_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i64 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %splat, %va ret %vc } define @icmp_sge_vi_nxv8i64_2( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -1 ; CHECK-NEXT: ret %head = insertelement poison, i64 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_sge_vi_nxv8i64_3( %va) { ; CHECK-LABEL: icmp_sge_vi_nxv8i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sge %va, %splat ret %vc } define @icmp_slt_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_slt_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmslt.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc } define @icmp_slt_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_slt_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmslt.vv v0, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_slt_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmslt.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_xv_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_slt_xv_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmslt.vv v0, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_slt_xv_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsgt.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %splat, %va ret %vc } define @icmp_slt_vi_nxv8i64_0( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -16 ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i64 -16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_vi_nxv8i64_1( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -16 ; CHECK-NEXT: ret %head = insertelement poison, i64 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_iv_nxv8i64_1( %va) { ; CHECK-LABEL: icmp_slt_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement poison, i64 -15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %splat, %va ret %vc } define @icmp_slt_vi_nxv8i64_2( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: ret %head = insertelement poison, i64 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_slt_vi_nxv8i64_3( %va) { ; CHECK-LABEL: icmp_slt_vi_nxv8i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp slt %va, %splat ret %vc } define @icmp_sle_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_sle_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc } define @icmp_sle_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_sle_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsle.vv v0, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_sle_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmsle.vx v0, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %va, %splat ret %vc } define @icmp_sle_xv_nxv8i64( %va, i64 %b) { ; RV32-LABEL: icmp_sle_xv_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmsle.vv v0, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: icmp_sle_xv_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmv.v.x v16, a0 ; RV64-NEXT: vmsle.vv v0, v16, v8 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %splat, %va ret %vc } define @icmp_sle_vi_nxv8i64_0( %va) { ; CHECK-LABEL: icmp_sle_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i64 5, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = icmp sle %va, %splat ret %vc } ; Check a setcc with two constant splats, which would previously get stuck in ; an infinite loop. DAGCombine isn't clever enough to constant-fold ; splat_vectors but could continuously swap the operands, trying to put the ; splat on the RHS. define @icmp_eq_ii_nxv8i8() { ; CHECK-LABEL: icmp_eq_ii_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret %heada = insertelement poison, i8 5, i32 0 %splata = shufflevector %heada, poison, zeroinitializer %headb = insertelement poison, i8 2, i32 0 %splatb = shufflevector %headb, poison, zeroinitializer %vc = icmp eq %splata, %splatb ret %vc } ; This icmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR ; node. Ensure we correctly (custom) lower this. define @icmp_eq_vi_nx16i64( %va) { ; CHECK-LABEL: icmp_eq_vi_nx16i64: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v24, v16, 0 ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, ma ; CHECK-NEXT: vslideup.vx v0, v24, a0 ; CHECK-NEXT: ret %vc = icmp eq %va, zeroinitializer ret %vc }