# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=riscv32 -mattr=+v -riscv-enable-subreg-liveness -run-pass riscv-init-undef -run-pass machineverifier %s -o - | FileCheck %s --- | source_filename = "" target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" target triple = "riscv64" define @undef_early_clobber_chain(ptr %p) #0 { entry: %0 = tail call @llvm.riscv.vrgather.vx.nxv2f32.i64( undef, undef, i64 0, i64 0) ret %0 } declare @llvm.riscv.vrgather.vx.nxv2f32.i64(, , i64, i64) #1 attributes #0 = { "target-features"="+v" } attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) "target-features"="+v" } ... --- name: undef_early_clobber_chain alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false selected: false failedISel: false tracksRegLiveness: true hasWinCFI: false callsEHReturn: false callsUnwindInit: false hasEHCatchret: false hasEHScopes: false hasEHFunclets: false isOutlined: false debugInstrRef: false failsVerification: false tracksDebugUserValues: false registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: vr, preferred-register: '' } - { id: 2, class: vr, preferred-register: '' } - { id: 3, class: vr, preferred-register: '' } liveins: [] frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false hasPatchPoint: false stackSize: 0 offsetAdjustment: 0 maxAlignment: 1 adjustsStack: false hasCalls: false stackProtector: '' functionContext: '' maxCallFrameSize: 4294967295 cvBytesOfCalleeSavedRegisters: 0 hasOpaqueSPAdjustment: false hasVAStart: false hasMustTailInVarArgFunc: false hasTailCall: false localFrameSize: 0 savePoint: '' restorePoint: '' fixedStack: [] stack: [] entry_values: [] callSites: [] debugValueSubstitutions: [] constants: [] machineFunctionInfo: varArgsFrameIndex: 0 varArgsSaveSize: 0 body: | bb.0.entry: ; CHECK-LABEL: name: undef_early_clobber_chain ; CHECK: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef [[DEF]], [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY %1 ; CHECK-NEXT: PseudoRET implicit $v8 %2:vr = IMPLICIT_DEF dead $x0 = PseudoVSETIVLI 0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef %2, undef %2, 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype $v8 = COPY %1 PseudoRET implicit $v8 ...