; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ ; RUN: -verify-machineinstrs | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ ; RUN: -verify-machineinstrs | FileCheck %s declare @llvm.riscv.vcompress.nxv1i8( , , , iXLen); define @intrinsic_vcompress_vm_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv1i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv2i8( , , , iXLen); define @intrinsic_vcompress_vm_nxv2i8_nxv2i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv2i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv4i8( , , , iXLen); define @intrinsic_vcompress_vm_nxv4i8_nxv4i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv4i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv8i8( , , , iXLen); define @intrinsic_vcompress_vm_nxv8i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv8i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv16i8( , , , iXLen); define @intrinsic_vcompress_vm_nxv16i8_nxv16i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv16i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv32i8( , , , iXLen); define @intrinsic_vcompress_vm_nxv32i8_nxv32i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma ; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv32i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv64i8( , , , iXLen); define @intrinsic_vcompress_vm_nxv64i8_nxv64i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma ; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv64i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv1i16( , , , iXLen); define @intrinsic_vcompress_vm_nxv1i16_nxv1i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv1i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv2i16( , , , iXLen); define @intrinsic_vcompress_vm_nxv2i16_nxv2i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv2i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv4i16( , , , iXLen); define @intrinsic_vcompress_vm_nxv4i16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv4i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv8i16( , , , iXLen); define @intrinsic_vcompress_vm_nxv8i16_nxv8i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv8i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv16i16( , , , iXLen); define @intrinsic_vcompress_vm_nxv16i16_nxv16i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv16i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv32i16( , , , iXLen); define @intrinsic_vcompress_vm_nxv32i16_nxv32i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma ; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv32i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv1i32( , , , iXLen); define @intrinsic_vcompress_vm_nxv1i32_nxv1i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv1i32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv2i32( , , , iXLen); define @intrinsic_vcompress_vm_nxv2i32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv2i32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv4i32( , , , iXLen); define @intrinsic_vcompress_vm_nxv4i32_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv4i32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv8i32( , , , iXLen); define @intrinsic_vcompress_vm_nxv8i32_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv8i32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv16i32( , , , iXLen); define @intrinsic_vcompress_vm_nxv16i32_nxv16i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma ; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv16i32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv1i64( , , , iXLen); define @intrinsic_vcompress_vm_nxv1i64_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv1i64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv2i64( , , , iXLen); define @intrinsic_vcompress_vm_nxv2i64_nxv2i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv2i64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv4i64( , , , iXLen); define @intrinsic_vcompress_vm_nxv4i64_nxv4i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv4i64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv8i64( , , , iXLen); define @intrinsic_vcompress_vm_nxv8i64_nxv8i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma ; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv8i64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv1f16( , , , iXLen); define @intrinsic_vcompress_vm_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv1f16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv2f16( , , , iXLen); define @intrinsic_vcompress_vm_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv2f16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv4f16( , , , iXLen); define @intrinsic_vcompress_vm_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv4f16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv8f16( , , , iXLen); define @intrinsic_vcompress_vm_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv8f16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv16f16( , , , iXLen); define @intrinsic_vcompress_vm_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv16f16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv32f16( , , , iXLen); define @intrinsic_vcompress_vm_nxv32f16_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma ; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv32f16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv1f32( , , , iXLen); define @intrinsic_vcompress_vm_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv1f32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv2f32( , , , iXLen); define @intrinsic_vcompress_vm_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv2f32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv4f32( , , , iXLen); define @intrinsic_vcompress_vm_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv4f32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv8f32( , , , iXLen); define @intrinsic_vcompress_vm_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv8f32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv16f32( , , , iXLen); define @intrinsic_vcompress_vm_nxv16f32_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma ; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv16f32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv1f64( , , , iXLen); define @intrinsic_vcompress_vm_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv1f64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv2f64( , , , iXLen); define @intrinsic_vcompress_vm_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv2f64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv4f64( , , , iXLen); define @intrinsic_vcompress_vm_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv4f64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vcompress.nxv8f64( , , , iXLen); define @intrinsic_vcompress_vm_nxv8f64_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma ; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vcompress.nxv8f64( %0, %1, %2, iXLen %3) ret %a }