; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V ; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V ; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X define @vdivu_vv_nxv1i8( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv1i8( %va, i8 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv1i8_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } ; Test V/1 to see if we can optimize it away for scalable vectors. define @vdivu_vi_nxv1i8_1( %va) { ; CHECK-LABEL: vdivu_vi_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %head = insertelement poison, i8 1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } ; Test 0/V to see if we can optimize it away for scalable vectors. define @vdivu_iv_nxv1i8_0( %va) { ; CHECK-LABEL: vdivu_iv_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: ret %head = insertelement poison, i8 0, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %splat, %va ret %vc } define @vdivu_vv_nxv2i8( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv2i8( %va, i8 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv2i8_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv4i8( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv4i8( %va, i8 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv4i8_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv8i8( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv8i8( %va, i8 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv8i8_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv16i8( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv16i8( %va, i8 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv16i8_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv32i8( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv32i8( %va, i8 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv32i8_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv64i8( %va, i8 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv64i8_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 33 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret %head = insertelement poison, i8 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv1i16( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv1i16( %va, i16 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv1i16_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement poison, i16 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv2i16( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv2i16( %va, i16 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv2i16_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement poison, i16 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv4i16( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv4i16( %va, i16 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv4i16_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement poison, i16 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv8i16( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv8i16( %va, i16 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv8i16_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement poison, i16 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv16i16( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv16i16( %va, i16 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv16i16_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement poison, i16 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv32i16( %va, i16 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv32i16_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 2 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret %head = insertelement poison, i16 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv1i32( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv1i32( %va, i32 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv1i32_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement poison, i32 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv2i32( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv2i32( %va, i32 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv2i32_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement poison, i32 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv4i32( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv4i32( %va, i32 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv4i32_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement poison, i32 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv8i32( %va, i32 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv8i32_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement poison, i32 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv16i32( %va, i32 signext %b) { ; CHECK-LABEL: vdivu_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv16i32_0( %va) { ; CHECK-LABEL: vdivu_vi_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 131072 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret %head = insertelement poison, i32 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vv_nxv1i64( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv1i64( %va, i64 %b) { ; RV32-LABEL: vdivu_vx_nxv1i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vdivu_vx_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vdivu.vx v8, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv1i64_0( %va) { ; RV32-V-LABEL: vdivu_vi_nxv1i64_0: ; RV32-V: # %bb.0: ; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-V-NEXT: vlse64.v v9, (a0), zero ; RV32-V-NEXT: vmulhu.vv v8, v8, v9 ; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: vsrl.vx v8, v8, a0 ; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: ret ; ; ZVE64X-LABEL: vdivu_vi_nxv1i64_0: ; ZVE64X: # %bb.0: ; ZVE64X-NEXT: li a0, -7 ; ZVE64X-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; ZVE64X-NEXT: vdivu.vx v8, v8, a0 ; ZVE64X-NEXT: ret ; ; RV64-V-LABEL: vdivu_vi_nxv1i64_0: ; RV64-V: # %bb.0: ; RV64-V-NEXT: li a0, 1 ; RV64-V-NEXT: slli a0, a0, 61 ; RV64-V-NEXT: addi a0, a0, 1 ; RV64-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-V-NEXT: vmulhu.vx v8, v8, a0 ; RV64-V-NEXT: li a0, 61 ; RV64-V-NEXT: vsrl.vx v8, v8, a0 ; RV64-V-NEXT: ret %head = insertelement poison, i64 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv1i64_1( %va) { ; CHECK-LABEL: vdivu_vi_nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 1 ; CHECK-NEXT: ret %head = insertelement poison, i64 2, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } ; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 define @vdivu_vi_nxv1i64_2( %va, %vb) { ; CHECK-LABEL: vdivu_vi_nxv1i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vi v9, v9, 4 ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = shl %splat, %vb %vd = udiv %va, %vc ret %vd } define @vdivu_vv_nxv2i64( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv2i64( %va, i64 %b) { ; RV32-LABEL: vdivu_vx_nxv2i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vdivu_vx_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV64-NEXT: vdivu.vx v8, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv2i64_0( %va) { ; RV32-V-LABEL: vdivu_vi_nxv2i64_0: ; RV32-V: # %bb.0: ; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-V-NEXT: vlse64.v v10, (a0), zero ; RV32-V-NEXT: vmulhu.vv v8, v8, v10 ; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: vsrl.vx v8, v8, a0 ; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: ret ; ; ZVE64X-LABEL: vdivu_vi_nxv2i64_0: ; ZVE64X: # %bb.0: ; ZVE64X-NEXT: li a0, -7 ; ZVE64X-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; ZVE64X-NEXT: vdivu.vx v8, v8, a0 ; ZVE64X-NEXT: ret ; ; RV64-V-LABEL: vdivu_vi_nxv2i64_0: ; RV64-V: # %bb.0: ; RV64-V-NEXT: li a0, 1 ; RV64-V-NEXT: slli a0, a0, 61 ; RV64-V-NEXT: addi a0, a0, 1 ; RV64-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV64-V-NEXT: vmulhu.vx v8, v8, a0 ; RV64-V-NEXT: li a0, 61 ; RV64-V-NEXT: vsrl.vx v8, v8, a0 ; RV64-V-NEXT: ret %head = insertelement poison, i64 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv2i64_1( %va) { ; CHECK-LABEL: vdivu_vi_nxv2i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 1 ; CHECK-NEXT: ret %head = insertelement poison, i64 2, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } ; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 define @vdivu_vi_nxv2i64_2( %va, %vb) { ; CHECK-LABEL: vdivu_vi_nxv2i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vadd.vi v10, v10, 4 ; CHECK-NEXT: vsrl.vv v8, v8, v10 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = shl %splat, %vb %vd = udiv %va, %vc ret %vd } define @vdivu_vv_nxv4i64( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv4i64( %va, i64 %b) { ; RV32-LABEL: vdivu_vx_nxv4i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vdivu_vx_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vdivu.vx v8, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv4i64_0( %va) { ; RV32-V-LABEL: vdivu_vi_nxv4i64_0: ; RV32-V: # %bb.0: ; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-V-NEXT: vlse64.v v12, (a0), zero ; RV32-V-NEXT: vmulhu.vv v8, v8, v12 ; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: vsrl.vx v8, v8, a0 ; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: ret ; ; ZVE64X-LABEL: vdivu_vi_nxv4i64_0: ; ZVE64X: # %bb.0: ; ZVE64X-NEXT: li a0, -7 ; ZVE64X-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; ZVE64X-NEXT: vdivu.vx v8, v8, a0 ; ZVE64X-NEXT: ret ; ; RV64-V-LABEL: vdivu_vi_nxv4i64_0: ; RV64-V: # %bb.0: ; RV64-V-NEXT: li a0, 1 ; RV64-V-NEXT: slli a0, a0, 61 ; RV64-V-NEXT: addi a0, a0, 1 ; RV64-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-V-NEXT: vmulhu.vx v8, v8, a0 ; RV64-V-NEXT: li a0, 61 ; RV64-V-NEXT: vsrl.vx v8, v8, a0 ; RV64-V-NEXT: ret %head = insertelement poison, i64 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv4i64_1( %va) { ; CHECK-LABEL: vdivu_vi_nxv4i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 1 ; CHECK-NEXT: ret %head = insertelement poison, i64 2, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } ; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 define @vdivu_vi_nxv4i64_2( %va, %vb) { ; CHECK-LABEL: vdivu_vi_nxv4i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vadd.vi v12, v12, 4 ; CHECK-NEXT: vsrl.vv v8, v8, v12 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = shl %splat, %vb %vd = udiv %va, %vc ret %vd } define @vdivu_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc } define @vdivu_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: vdivu_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vdivu_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vdivu.vx v8, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv8i64_0( %va) { ; RV32-V-LABEL: vdivu_vi_nxv8i64_0: ; RV32-V: # %bb.0: ; RV32-V-NEXT: addi sp, sp, -16 ; RV32-V-NEXT: .cfi_def_cfa_offset 16 ; RV32-V-NEXT: lui a0, 131072 ; RV32-V-NEXT: sw a0, 12(sp) ; RV32-V-NEXT: li a0, 1 ; RV32-V-NEXT: sw a0, 8(sp) ; RV32-V-NEXT: addi a0, sp, 8 ; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-V-NEXT: vlse64.v v16, (a0), zero ; RV32-V-NEXT: vmulhu.vv v8, v8, v16 ; RV32-V-NEXT: li a0, 61 ; RV32-V-NEXT: vsrl.vx v8, v8, a0 ; RV32-V-NEXT: addi sp, sp, 16 ; RV32-V-NEXT: ret ; ; ZVE64X-LABEL: vdivu_vi_nxv8i64_0: ; ZVE64X: # %bb.0: ; ZVE64X-NEXT: li a0, -7 ; ZVE64X-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; ZVE64X-NEXT: vdivu.vx v8, v8, a0 ; ZVE64X-NEXT: ret ; ; RV64-V-LABEL: vdivu_vi_nxv8i64_0: ; RV64-V: # %bb.0: ; RV64-V-NEXT: li a0, 1 ; RV64-V-NEXT: slli a0, a0, 61 ; RV64-V-NEXT: addi a0, a0, 1 ; RV64-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-V-NEXT: vmulhu.vx v8, v8, a0 ; RV64-V-NEXT: li a0, 61 ; RV64-V-NEXT: vsrl.vx v8, v8, a0 ; RV64-V-NEXT: ret %head = insertelement poison, i64 -7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } define @vdivu_vi_nxv8i64_1( %va) { ; CHECK-LABEL: vdivu_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 1 ; CHECK-NEXT: ret %head = insertelement poison, i64 2, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = udiv %va, %splat ret %vc } ; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2 define @vdivu_vi_nxv8i64_2( %va, %vb) { ; CHECK-LABEL: vdivu_vi_nxv8i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v16, v16, 4 ; CHECK-NEXT: vsrl.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = shl %splat, %vb %vd = udiv %va, %vc ret %vd } define @vdivu_vv_mask_nxv8i32( %va, %vb, %mask) { ; CHECK-LABEL: vdivu_vv_mask_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv.v.i v16, 1 ; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0 ; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %head = insertelement poison, i32 1, i32 0 %one = shufflevector %head, poison, zeroinitializer %vs = select %mask, %vb, %one %vc = udiv %va, %vs ret %vc } define @vdivu_vx_mask_nxv8i32( %va, i32 signext %b, %mask) { ; CHECK-LABEL: vdivu_vx_mask_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv.v.i v12, 1 ; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0 ; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %head1 = insertelement poison, i32 1, i32 0 %one = shufflevector %head1, poison, zeroinitializer %head2 = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head2, poison, zeroinitializer %vs = select %mask, %splat, %one %vc = udiv %va, %vs ret %vc } define @vdivu_vi_mask_nxv8i32( %va, %mask) { ; CHECK-LABEL: vdivu_vi_mask_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a0, 149797 ; CHECK-NEXT: addi a0, a0, -1755 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vmulhu.vx v12, v8, a0 ; CHECK-NEXT: vsub.vv v16, v8, v12 ; CHECK-NEXT: vsrl.vi v16, v16, 1 ; CHECK-NEXT: vadd.vv v12, v16, v12 ; CHECK-NEXT: vsrl.vi v8, v12, 2, v0.t ; CHECK-NEXT: ret %head1 = insertelement poison, i32 1, i32 0 %one = shufflevector %head1, poison, zeroinitializer %head2 = insertelement poison, i32 7, i32 0 %splat = shufflevector %head2, poison, zeroinitializer %vs = select %mask, %splat, %one %vc = udiv %va, %vs ret %vc }