; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple riscv32 -mattr=+m,+f,+d,+v,+zfh,+zvfh < %s | FileCheck %s ; RUN: llc -mtriple riscv64 -mattr=+m,+f,+d,+v,+zfh,+zvfh < %s | FileCheck %s ; Tests assume VLEN=128 or vscale_range_min=2. declare @llvm.experimental.vector.splice.nxv1i1(, , i32) define @splice_nxv1i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i1_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vslidedown.vx v9, v9, a0 ; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i1( %a, %b, i32 -1) ret %res } define @splice_nxv1i1_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i1_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vslidedown.vi v9, v9, 1 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i1( %a, %b, i32 1) ret %res } declare @llvm.experimental.vector.splice.nxv2i1(, , i32) define @splice_nxv2i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i1_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vslidedown.vx v9, v9, a0 ; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i1( %a, %b, i32 -1) ret %res } define @splice_nxv2i1_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i1_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vi v9, v9, 3 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i1( %a, %b, i32 3) ret %res } declare @llvm.experimental.vector.splice.nxv4i1(, , i32) define @splice_nxv4i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i1_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vslidedown.vx v9, v9, a0 ; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i1( %a, %b, i32 -1) ret %res } define @splice_nxv4i1_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i1_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vslidedown.vi v9, v9, 7 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i1( %a, %b, i32 7) ret %res } declare @llvm.experimental.vector.splice.nxv8i1(, , i32) define @splice_nxv8i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i1_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vslidedown.vx v9, v9, a0 ; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i1( %a, %b, i32 -1) ret %res } define @splice_nxv8i1_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i1_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v9, v10, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v9, v9, 15 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i1( %a, %b, i32 15) ret %res } declare @llvm.experimental.vector.splice.nxv16i1(, , i32) define @splice_nxv16i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i1_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v12, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i1( %a, %b, i32 -1) ret %res } define @splice_nxv16i1_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i1_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v12, v10, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i1( %a, %b, i32 31) ret %res } declare @llvm.experimental.vector.splice.nxv32i1(, , i32) define @splice_nxv32i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i1_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v16, v12, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v8, v12, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32i1( %a, %b, i32 -1) ret %res } define @splice_nxv32i1_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i1_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmerge.vim v16, v12, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -63 ; CHECK-NEXT: li a1, 63 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v16, v16, a1 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v12, 1, v0 ; CHECK-NEXT: vslideup.vx v16, v8, a0 ; CHECK-NEXT: vand.vi v8, v16, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32i1( %a, %b, i32 63) ret %res } declare @llvm.experimental.vector.splice.nxv64i1(, , i32) define @splice_nxv64i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv64i1_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v9, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vmv.v.i v24, 0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v16, v24, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmerge.vim v8, v24, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv64i1( %a, %b, i32 -1) ret %res } define @splice_nxv64i1_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv64i1_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmerge.vim v24, v16, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -127 ; CHECK-NEXT: li a1, 127 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v24, v24, a1 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v16, 1, v0 ; CHECK-NEXT: vslideup.vx v24, v8, a0 ; CHECK-NEXT: vand.vi v8, v24, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv64i1( %a, %b, i32 127) ret %res } declare @llvm.experimental.vector.splice.nxv1i8(, , i32) define @splice_nxv1i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i8( %a, %b, i32 0) ret %res } define @splice_nxv1i8_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i8_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i8( %a, %b, i32 -1) ret %res } define @splice_nxv1i8_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i8_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i8( %a, %b, i32 -2) ret %res } define @splice_nxv1i8_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i8_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i8( %a, %b, i32 1) ret %res } declare @llvm.experimental.vector.splice.nxv2i8(, , i32) define @splice_nxv2i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i8( %a, %b, i32 0) ret %res } define @splice_nxv2i8_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i8_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i8( %a, %b, i32 -1) ret %res } define @splice_nxv2i8_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i8_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i8( %a, %b, i32 -4) ret %res } define @splice_nxv2i8_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i8_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i8( %a, %b, i32 3) ret %res } declare @llvm.experimental.vector.splice.nxv4i8(, , i32) define @splice_nxv4i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i8( %a, %b, i32 0) ret %res } define @splice_nxv4i8_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i8_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i8( %a, %b, i32 -1) ret %res } define @splice_nxv4i8_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i8_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 8 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i8( %a, %b, i32 -8) ret %res } define @splice_nxv4i8_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i8_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i8( %a, %b, i32 7) ret %res } declare @llvm.experimental.vector.splice.nxv8i8(, , i32) define @splice_nxv8i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i8( %a, %b, i32 0) ret %res } define @splice_nxv8i8_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i8_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i8( %a, %b, i32 -1) ret %res } define @splice_nxv8i8_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i8_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 16 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i8( %a, %b, i32 -16) ret %res } define @splice_nxv8i8_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i8_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i8( %a, %b, i32 15) ret %res } declare @llvm.experimental.vector.splice.nxv16i8(, , i32) define @splice_nxv16i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 0) ret %res } define @splice_nxv16i8_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i8_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -1) ret %res } define @splice_nxv16i8_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i8_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -32 ; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -32) ret %res } define @splice_nxv16i8_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i8_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 31) ret %res } declare @llvm.experimental.vector.splice.nxv32i8(, , i32) define @splice_nxv32i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32i8( %a, %b, i32 0) ret %res } define @splice_nxv32i8_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i8_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32i8( %a, %b, i32 -1) ret %res } define @splice_nxv32i8_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i8_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -64 ; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32i8( %a, %b, i32 -64) ret %res } define @splice_nxv32i8_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i8_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -63 ; CHECK-NEXT: li a1, 63 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32i8( %a, %b, i32 63) ret %res } declare @llvm.experimental.vector.splice.nxv64i8(, , i32) define @splice_nxv64i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv64i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv64i8( %a, %b, i32 0) ret %res } define @splice_nxv64i8_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv64i8_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv64i8( %a, %b, i32 -1) ret %res } define @splice_nxv64i8_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv64i8_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -128 ; CHECK-NEXT: li a1, 128 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv64i8( %a, %b, i32 -128) ret %res } define @splice_nxv64i8_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv64i8_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -127 ; CHECK-NEXT: li a1, 127 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv64i8( %a, %b, i32 127) ret %res } declare @llvm.experimental.vector.splice.nxv1i16(, , i32) define @splice_nxv1i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i16( %a, %b, i32 0) ret %res } define @splice_nxv1i16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i16( %a, %b, i32 -1) ret %res } define @splice_nxv1i16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i16( %a, %b, i32 -2) ret %res } define @splice_nxv1i16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i16( %a, %b, i32 1) ret %res } declare @llvm.experimental.vector.splice.nxv2i16(, , i32) define @splice_nxv2i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i16( %a, %b, i32 0) ret %res } define @splice_nxv2i16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i16( %a, %b, i32 -1) ret %res } define @splice_nxv2i16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i16( %a, %b, i32 -4) ret %res } define @splice_nxv2i16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i16( %a, %b, i32 3) ret %res } declare @llvm.experimental.vector.splice.nxv4i16(, , i32) define @splice_nxv4i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i16( %a, %b, i32 0) ret %res } define @splice_nxv4i16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i16( %a, %b, i32 -1) ret %res } define @splice_nxv4i16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 8 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i16( %a, %b, i32 -8) ret %res } define @splice_nxv4i16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i16( %a, %b, i32 7) ret %res } declare @llvm.experimental.vector.splice.nxv8i16(, , i32) define @splice_nxv8i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 0) ret %res } define @splice_nxv8i16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 -1) ret %res } define @splice_nxv8i16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 16 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 -16) ret %res } define @splice_nxv8i16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 15) ret %res } declare @llvm.experimental.vector.splice.nxv16i16(, , i32) define @splice_nxv16i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i16( %a, %b, i32 0) ret %res } define @splice_nxv16i16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i16( %a, %b, i32 -1) ret %res } define @splice_nxv16i16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -32 ; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i16( %a, %b, i32 -32) ret %res } define @splice_nxv16i16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i16( %a, %b, i32 31) ret %res } declare @llvm.experimental.vector.splice.nxv32i16(, , i32) define @splice_nxv32i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32i16( %a, %b, i32 0) ret %res } define @splice_nxv32i16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32i16( %a, %b, i32 -1) ret %res } define @splice_nxv32i16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -64 ; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32i16( %a, %b, i32 -64) ret %res } define @splice_nxv32i16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -63 ; CHECK-NEXT: li a1, 63 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32i16( %a, %b, i32 63) ret %res } declare @llvm.experimental.vector.splice.nxv1i32(, , i32) define @splice_nxv1i32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i32( %a, %b, i32 0) ret %res } define @splice_nxv1i32_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i32_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i32( %a, %b, i32 -1) ret %res } define @splice_nxv1i32_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i32_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i32( %a, %b, i32 -2) ret %res } define @splice_nxv1i32_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i32_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i32( %a, %b, i32 1) ret %res } declare @llvm.experimental.vector.splice.nxv2i32(, , i32) define @splice_nxv2i32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i32( %a, %b, i32 0) ret %res } define @splice_nxv2i32_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i32_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i32( %a, %b, i32 -1) ret %res } define @splice_nxv2i32_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i32_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i32( %a, %b, i32 -4) ret %res } define @splice_nxv2i32_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i32_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i32( %a, %b, i32 3) ret %res } declare @llvm.experimental.vector.splice.nxv4i32(, , i32) define @splice_nxv4i32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 0) ret %res } define @splice_nxv4i32_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i32_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 -1) ret %res } define @splice_nxv4i32_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i32_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 8 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 -8) ret %res } define @splice_nxv4i32_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i32_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 7) ret %res } declare @llvm.experimental.vector.splice.nxv8i32(, , i32) define @splice_nxv8i32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i32( %a, %b, i32 0) ret %res } define @splice_nxv8i32_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i32_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i32( %a, %b, i32 -1) ret %res } define @splice_nxv8i32_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i32_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 16 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i32( %a, %b, i32 -16) ret %res } define @splice_nxv8i32_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i32_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i32( %a, %b, i32 15) ret %res } declare @llvm.experimental.vector.splice.nxv16i32(, , i32) define @splice_nxv16i32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i32( %a, %b, i32 0) ret %res } define @splice_nxv16i32_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i32_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i32( %a, %b, i32 -1) ret %res } define @splice_nxv16i32_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i32_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -32 ; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i32( %a, %b, i32 -32) ret %res } define @splice_nxv16i32_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i32_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16i32( %a, %b, i32 31) ret %res } declare @llvm.experimental.vector.splice.nxv1i64(, , i32) define @splice_nxv1i64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i64( %a, %b, i32 0) ret %res } define @splice_nxv1i64_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i64_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i64( %a, %b, i32 -1) ret %res } define @splice_nxv1i64_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i64_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i64( %a, %b, i32 -2) ret %res } define @splice_nxv1i64_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i64_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1i64( %a, %b, i32 1) ret %res } declare @llvm.experimental.vector.splice.nxv2i64(, , i32) define @splice_nxv2i64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 0) ret %res } define @splice_nxv2i64_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i64_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 -1) ret %res } define @splice_nxv2i64_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i64_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 4 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 -4) ret %res } define @splice_nxv2i64_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i64_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 3) ret %res } declare @llvm.experimental.vector.splice.nxv4i64(, , i32) define @splice_nxv4i64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i64( %a, %b, i32 0) ret %res } define @splice_nxv4i64_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i64_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i64( %a, %b, i32 -1) ret %res } define @splice_nxv4i64_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i64_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 8 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i64( %a, %b, i32 -8) ret %res } define @splice_nxv4i64_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i64_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4i64( %a, %b, i32 7) ret %res } declare @llvm.experimental.vector.splice.nxv8i64(, , i32) define @splice_nxv8i64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i64( %a, %b, i32 0) ret %res } define @splice_nxv8i64_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i64_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i64( %a, %b, i32 -1) ret %res } define @splice_nxv8i64_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i64_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 16 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i64( %a, %b, i32 -16) ret %res } define @splice_nxv8i64_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i64_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8i64( %a, %b, i32 15) ret %res } declare @llvm.experimental.vector.splice.nxv1f16(, , i32) define @splice_nxv1f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f16( %a, %b, i32 0) ret %res } define @splice_nxv1f16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f16( %a, %b, i32 -1) ret %res } define @splice_nxv1f16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f16( %a, %b, i32 -2) ret %res } define @splice_nxv1f16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f16( %a, %b, i32 1) ret %res } declare @llvm.experimental.vector.splice.nxv2f16(, , i32) define @splice_nxv2f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 0) ret %res } define @splice_nxv2f16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 -1) ret %res } define @splice_nxv2f16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 -4) ret %res } define @splice_nxv2f16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 3) ret %res } declare @llvm.experimental.vector.splice.nxv4f16(, , i32) define @splice_nxv4f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 0) ret %res } define @splice_nxv4f16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 -1) ret %res } define @splice_nxv4f16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 8 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 -8) ret %res } define @splice_nxv4f16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 7) ret %res } declare @llvm.experimental.vector.splice.nxv8f16(, , i32) define @splice_nxv8f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 0) ret %res } define @splice_nxv8f16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 -1) ret %res } define @splice_nxv8f16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 16 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 -16) ret %res } define @splice_nxv8f16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 15) ret %res } declare @llvm.experimental.vector.splice.nxv16f16(, , i32) define @splice_nxv16f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16f16( %a, %b, i32 0) ret %res } define @splice_nxv16f16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16f16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16f16( %a, %b, i32 -1) ret %res } define @splice_nxv16f16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16f16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -32 ; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16f16( %a, %b, i32 -32) ret %res } define @splice_nxv16f16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16f16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16f16( %a, %b, i32 31) ret %res } declare @llvm.experimental.vector.splice.nxv32f16(, , i32) define @splice_nxv32f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32f16( %a, %b, i32 0) ret %res } define @splice_nxv32f16_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32f16_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32f16( %a, %b, i32 -1) ret %res } define @splice_nxv32f16_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32f16_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -64 ; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32f16( %a, %b, i32 -64) ret %res } define @splice_nxv32f16_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32f16_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -63 ; CHECK-NEXT: li a1, 63 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv32f16( %a, %b, i32 63) ret %res } declare @llvm.experimental.vector.splice.nxv1f32(, , i32) define @splice_nxv1f32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f32( %a, %b, i32 0) ret %res } define @splice_nxv1f32_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f32_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f32( %a, %b, i32 -1) ret %res } define @splice_nxv1f32_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f32_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f32( %a, %b, i32 -2) ret %res } define @splice_nxv1f32_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f32_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f32( %a, %b, i32 1) ret %res } declare @llvm.experimental.vector.splice.nxv2f32(, , i32) define @splice_nxv2f32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 0) ret %res } define @splice_nxv2f32_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f32_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 -1) ret %res } define @splice_nxv2f32_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f32_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 -4) ret %res } define @splice_nxv2f32_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f32_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 3) ret %res } declare @llvm.experimental.vector.splice.nxv4f32(, , i32) define @splice_nxv4f32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 0) ret %res } define @splice_nxv4f32_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f32_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 -1) ret %res } define @splice_nxv4f32_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f32_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 8 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 -8) ret %res } define @splice_nxv4f32_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f32_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 7) ret %res } declare @llvm.experimental.vector.splice.nxv8f32(, , i32) define @splice_nxv8f32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f32( %a, %b, i32 0) ret %res } define @splice_nxv8f32_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f32_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f32( %a, %b, i32 -1) ret %res } define @splice_nxv8f32_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f32_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 16 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f32( %a, %b, i32 -16) ret %res } define @splice_nxv8f32_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f32_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f32( %a, %b, i32 15) ret %res } declare @llvm.experimental.vector.splice.nxv16f32(, , i32) define @splice_nxv16f32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16f32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16f32( %a, %b, i32 0) ret %res } define @splice_nxv16f32_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16f32_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16f32( %a, %b, i32 -1) ret %res } define @splice_nxv16f32_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16f32_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -32 ; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16f32( %a, %b, i32 -32) ret %res } define @splice_nxv16f32_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16f32_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv16f32( %a, %b, i32 31) ret %res } declare @llvm.experimental.vector.splice.nxv1f64(, , i32) define @splice_nxv1f64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f64( %a, %b, i32 0) ret %res } define @splice_nxv1f64_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f64_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f64( %a, %b, i32 -1) ret %res } define @splice_nxv1f64_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f64_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f64( %a, %b, i32 -2) ret %res } define @splice_nxv1f64_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f64_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv1f64( %a, %b, i32 1) ret %res } declare @llvm.experimental.vector.splice.nxv2f64(, , i32) define @splice_nxv2f64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 0) ret %res } define @splice_nxv2f64_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f64_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 -1) ret %res } define @splice_nxv2f64_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f64_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 4 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 -4) ret %res } define @splice_nxv2f64_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f64_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 3) ret %res } declare @llvm.experimental.vector.splice.nxv4f64(, , i32) define @splice_nxv4f64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f64( %a, %b, i32 0) ret %res } define @splice_nxv4f64_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f64_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f64( %a, %b, i32 -1) ret %res } define @splice_nxv4f64_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f64_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 8 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f64( %a, %b, i32 -8) ret %res } define @splice_nxv4f64_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f64_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv4f64( %a, %b, i32 7) ret %res } declare @llvm.experimental.vector.splice.nxv8f64(, , i32) define @splice_nxv8f64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f64( %a, %b, i32 0) ret %res } define @splice_nxv8f64_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f64_offset_negone: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f64( %a, %b, i32 -1) ret %res } define @splice_nxv8f64_offset_min( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f64_offset_min: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 16 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f64( %a, %b, i32 -16) ret %res } define @splice_nxv8f64_offset_max( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f64_offset_max: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret %res = call @llvm.experimental.vector.splice.nxv8f64( %a, %b, i32 15) ret %res } attributes #0 = { vscale_range(2,0) }