; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @isnan_nxv2f16( %x) { ; CHECK-LABEL: isnan_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: li a0, 768 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv2f16( %x, i32 3) ; nan ret %1 } define @isnan_nxv2f32( %x) { ; CHECK-LABEL: isnan_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: li a0, 927 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv2f32( %x, i32 639) ret %1 } define @isnan_nxv4f32( %x) { ; CHECK-LABEL: isnan_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: li a0, 768 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv4f32( %x, i32 3) ; nan ret %1 } define @isnan_nxv8f32( %x) { ; CHECK-LABEL: isnan_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: li a0, 512 ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv8f32( %x, i32 2) ret %1 } define @isnan_nxv16f32( %x) { ; CHECK-LABEL: isnan_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: li a0, 256 ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv16f32( %x, i32 1) ret %1 } define @isnormal_nxv2f64( %x) { ; CHECK-LABEL: isnormal_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: li a0, 129 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv2f64( %x, i32 516) ; 0x204 = "inf" ret %1 } define @isposinf_nxv4f64( %x) { ; CHECK-LABEL: isposinf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: li a0, 128 ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv4f64( %x, i32 512) ; 0x200 = "+inf" ret %1 } define @isneginf_nxv8f64( %x) { ; CHECK-LABEL: isneginf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vmseq.vi v0, v8, 1 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv8f64( %x, i32 4) ; "-inf" ret %1 } define @isfinite_nxv16f32( %x) { ; CHECK-LABEL: isfinite_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: li a0, 126 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv16f32( %x, i32 504) ; 0x1f8 = "finite" ret %1 } define @isposfinite_nxv16f32( %x) { ; CHECK-LABEL: isposfinite_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: li a0, 112 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv16f32( %x, i32 448) ; 0x1c0 = "+finite" ret %1 } define @isnegfinite_nxv16f32( %x) { ; CHECK-LABEL: isnegfinite_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vand.vi v8, v8, 14 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv16f32( %x, i32 56) ; 0x38 = "-finite" ret %1 } define @isnotfinite_nxv16f32( %x) { ; CHECK-LABEL: isnotfinite_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: li a0, 897 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %1 = call @llvm.is.fpclass.nxv16f32( %x, i32 519) ; 0x207 = "inf|nan" ret %1 } declare @llvm.is.fpclass.nxv2f16(, i32) declare @llvm.is.fpclass.nxv2f32(, i32) declare @llvm.is.fpclass.nxv4f32(, i32) declare @llvm.is.fpclass.nxv8f32(, i32) declare @llvm.is.fpclass.nxv16f32(, i32) declare @llvm.is.fpclass.nxv2f64(, i32) declare @llvm.is.fpclass.nxv4f64(, i32) declare @llvm.is.fpclass.nxv8f64(, i32)