; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfmax.nxv1f16.nxv1f16( , , , iXLen); define @intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv1f16.nxv1f16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv2f16.nxv2f16( , , , iXLen); define @intrinsic_vfmax_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv2f16.nxv2f16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv4f16.nxv4f16( , , , iXLen); define @intrinsic_vfmax_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv4f16.nxv4f16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv8f16.nxv8f16( , , , iXLen); define @intrinsic_vfmax_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv8f16.nxv8f16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vfmax.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv16f16.nxv16f16( , , , iXLen); define @intrinsic_vfmax_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv16f16.nxv16f16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vfmax.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv32f16.nxv32f16( , , , iXLen); define @intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv32f16.nxv32f16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv1f32.nxv1f32( , , , iXLen); define @intrinsic_vfmax_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv1f32.nxv1f32( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv2f32.nxv2f32( , , , iXLen); define @intrinsic_vfmax_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv2f32.nxv2f32( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv4f32.nxv4f32( , , , iXLen); define @intrinsic_vfmax_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv4f32.nxv4f32( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vfmax.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv8f32.nxv8f32( , , , iXLen); define @intrinsic_vfmax_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv8f32.nxv8f32( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vfmax.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv16f32.nxv16f32( , , , iXLen); define @intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv16f32.nxv16f32( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv1f64.nxv1f64( , , , iXLen); define @intrinsic_vfmax_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv1f64.nxv1f64( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv1f64.nxv1f64( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv1f64.nxv1f64( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv2f64.nxv2f64( , , , iXLen); define @intrinsic_vfmax_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv2f64.nxv2f64( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv2f64.nxv2f64( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vfmax.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv2f64.nxv2f64( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv4f64.nxv4f64( , , , iXLen); define @intrinsic_vfmax_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv4f64.nxv4f64( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv4f64.nxv4f64( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vfmax.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv4f64.nxv4f64( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv8f64.nxv8f64( , , , iXLen); define @intrinsic_vfmax_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv8f64.nxv8f64( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64( , , , , iXLen, iXLen); define @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv1f16.f16( , , half, iXLen); define @intrinsic_vfmax_vf_nxv1f16_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv1f16.f16( undef, %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv1f16.f16( , , half, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vfmax.vf v8, v9, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv1f16.f16( %0, %1, half %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv2f16.f16( , , half, iXLen); define @intrinsic_vfmax_vf_nxv2f16_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv2f16.f16( undef, %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv2f16.f16( , , half, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vfmax.vf v8, v9, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv2f16.f16( %0, %1, half %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv4f16.f16( , , half, iXLen); define @intrinsic_vfmax_vf_nxv4f16_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv4f16.f16( undef, %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv4f16.f16( , , half, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vfmax.vf v8, v9, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv4f16.f16( %0, %1, half %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv8f16.f16( , , half, iXLen); define @intrinsic_vfmax_vf_nxv8f16_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv8f16.f16( undef, %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv8f16.f16( , , half, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vfmax.vf v8, v10, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv8f16.f16( %0, %1, half %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv16f16.f16( , , half, iXLen); define @intrinsic_vfmax_vf_nxv16f16_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv16f16.f16( undef, %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv16f16.f16( , , half, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vfmax.vf v8, v12, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv16f16.f16( %0, %1, half %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv32f16.f16( , , half, iXLen); define @intrinsic_vfmax_vf_nxv32f16_nxv32f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv32f16.f16( undef, %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv32f16.f16( , , half, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vfmax.vf v8, v16, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv32f16.f16( %0, %1, half %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv1f32.f32( , , float, iXLen); define @intrinsic_vfmax_vf_nxv1f32_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv1f32.f32( undef, %0, float %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv1f32.f32( , , float, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vfmax.vf v8, v9, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv1f32.f32( %0, %1, float %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv2f32.f32( , , float, iXLen); define @intrinsic_vfmax_vf_nxv2f32_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv2f32.f32( undef, %0, float %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv2f32.f32( , , float, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vfmax.vf v8, v9, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv2f32.f32( %0, %1, float %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv4f32.f32( , , float, iXLen); define @intrinsic_vfmax_vf_nxv4f32_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv4f32.f32( undef, %0, float %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv4f32.f32( , , float, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vfmax.vf v8, v10, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv4f32.f32( %0, %1, float %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv8f32.f32( , , float, iXLen); define @intrinsic_vfmax_vf_nxv8f32_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv8f32.f32( undef, %0, float %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv8f32.f32( , , float, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vfmax.vf v8, v12, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv8f32.f32( %0, %1, float %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv16f32.f32( , , float, iXLen); define @intrinsic_vfmax_vf_nxv16f32_nxv16f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv16f32.f32( undef, %0, float %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv16f32.f32( , , float, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vfmax.vf v8, v16, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv16f32.f32( %0, %1, float %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv1f64.f64( , , double, iXLen); define @intrinsic_vfmax_vf_nxv1f64_nxv1f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv1f64.f64( undef, %0, double %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv1f64.f64( , , double, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vfmax.vf v8, v9, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv1f64.f64( %0, %1, double %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv2f64.f64( , , double, iXLen); define @intrinsic_vfmax_vf_nxv2f64_nxv2f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv2f64.f64( undef, %0, double %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv2f64.f64( , , double, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vfmax.vf v8, v10, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv2f64.f64( %0, %1, double %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv4f64.f64( , , double, iXLen); define @intrinsic_vfmax_vf_nxv4f64_nxv4f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv4f64.f64( undef, %0, double %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv4f64.f64( , , double, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vfmax.vf v8, v12, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv4f64.f64( %0, %1, double %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vfmax.nxv8f64.f64( , , double, iXLen); define @intrinsic_vfmax_vf_nxv8f64_nxv8f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmax.vf v8, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.nxv8f64.f64( undef, %0, double %1, iXLen %2) ret %a } declare @llvm.riscv.vfmax.mask.nxv8f64.f64( , , double, , iXLen, iXLen); define @intrinsic_vfmax_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vfmax.vf v8, v16, fa0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmax.mask.nxv8f64.f64( %0, %1, double %2, %3, iXLen %4, iXLen 1) ret %a }