; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare @llvm.minnum.nxv1f16(, ) define @vfmin_nxv1f16_vv( %a, %b) { ; ZVFH-LABEL: vfmin_nxv1f16_vv: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfmin.vv v8, v8, v9 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv1f16_vv: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret %v = call @llvm.minnum.nxv1f16( %a, %b) ret %v } define @vfmin_nxv1f16_vf( %a, half %b) { ; ZVFH-LABEL: vfmin_nxv1f16_vf: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfmin.vf v8, v8, fa0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv1f16_vf: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv1f16( %a, %splat) ret %v } declare @llvm.minnum.nxv2f16(, ) define @vfmin_nxv2f16_vv( %a, %b) { ; ZVFH-LABEL: vfmin_nxv2f16_vv: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfmin.vv v8, v8, v9 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv2f16_vv: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret %v = call @llvm.minnum.nxv2f16( %a, %b) ret %v } define @vfmin_nxv2f16_vf( %a, half %b) { ; ZVFH-LABEL: vfmin_nxv2f16_vf: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfmin.vf v8, v8, fa0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv2f16_vf: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmv.v.f v9, fa5 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv2f16( %a, %splat) ret %v } declare @llvm.minnum.nxv4f16(, ) define @vfmin_nxv4f16_vv( %a, %b) { ; ZVFH-LABEL: vfmin_nxv4f16_vv: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfmin.vv v8, v8, v9 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv4f16_vv: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret %v = call @llvm.minnum.nxv4f16( %a, %b) ret %v } define @vfmin_nxv4f16_vf( %a, half %b) { ; ZVFH-LABEL: vfmin_nxv4f16_vf: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfmin.vf v8, v8, fa0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv4f16_vf: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmv.v.f v10, fa5 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v10, v10, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv4f16( %a, %splat) ret %v } declare @llvm.minnum.nxv8f16(, ) define @vfmin_nxv8f16_vv( %a, %b) { ; ZVFH-LABEL: vfmin_nxv8f16_vv: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFH-NEXT: vfmin.vv v8, v8, v10 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv8f16_vv: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret %v = call @llvm.minnum.nxv8f16( %a, %b) ret %v } define @vfmin_nxv8f16_vf( %a, half %b) { ; ZVFH-LABEL: vfmin_nxv8f16_vf: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFH-NEXT: vfmin.vf v8, v8, fa0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv8f16_vf: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v12, v12, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv8f16( %a, %splat) ret %v } declare @llvm.minnum.nxv16f16(, ) define @vfmin_nxv16f16_vv( %a, %b) { ; ZVFH-LABEL: vfmin_nxv16f16_vv: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFH-NEXT: vfmin.vv v8, v8, v12 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv16f16_vv: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret %v = call @llvm.minnum.nxv16f16( %a, %b) ret %v } define @vfmin_nxv16f16_vf( %a, half %b) { ; ZVFH-LABEL: vfmin_nxv16f16_vf: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFH-NEXT: vfmin.vf v8, v8, fa0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv16f16_vf: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv16f16( %a, %splat) ret %v } declare @llvm.minnum.nxv32f16(, ) define @vfmin_nxv32f16_vv( %a, %b) { ; ZVFH-LABEL: vfmin_nxv32f16_vv: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; ZVFH-NEXT: vfmin.vv v8, v8, v16 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv32f16_vv: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v24, v0, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret %v = call @llvm.minnum.nxv32f16( %a, %b) ret %v } define @vfmin_nxv32f16_vf( %a, half %b) { ; ZVFH-LABEL: vfmin_nxv32f16_vf: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; ZVFH-NEXT: vfmin.vf v8, v8, fa0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfmin_nxv32f16_vf: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v24, v16 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v16, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v16, v0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv32f16( %a, %splat) ret %v } declare @llvm.minnum.nxv1f32(, ) define @vfmin_nxv1f32_vv( %a, %b) { ; CHECK-LABEL: vfmin_nxv1f32_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.minnum.nxv1f32( %a, %b) ret %v } define @vfmin_nxv1f32_vf( %a, float %b) { ; CHECK-LABEL: vfmin_nxv1f32_vf: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfmin.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement poison, float %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv1f32( %a, %splat) ret %v } declare @llvm.minnum.nxv2f32(, ) define @vfmin_nxv2f32_vv( %a, %b) { ; CHECK-LABEL: vfmin_nxv2f32_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.minnum.nxv2f32( %a, %b) ret %v } define @vfmin_nxv2f32_vf( %a, float %b) { ; CHECK-LABEL: vfmin_nxv2f32_vf: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vfmin.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement poison, float %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv2f32( %a, %splat) ret %v } declare @llvm.minnum.nxv4f32(, ) define @vfmin_nxv4f32_vv( %a, %b) { ; CHECK-LABEL: vfmin_nxv4f32_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v10 ; CHECK-NEXT: ret %v = call @llvm.minnum.nxv4f32( %a, %b) ret %v } define @vfmin_nxv4f32_vf( %a, float %b) { ; CHECK-LABEL: vfmin_nxv4f32_vf: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vfmin.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement poison, float %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv4f32( %a, %splat) ret %v } declare @llvm.minnum.nxv8f32(, ) define @vfmin_nxv8f32_vv( %a, %b) { ; CHECK-LABEL: vfmin_nxv8f32_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v12 ; CHECK-NEXT: ret %v = call @llvm.minnum.nxv8f32( %a, %b) ret %v } define @vfmin_nxv8f32_vf( %a, float %b) { ; CHECK-LABEL: vfmin_nxv8f32_vf: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vfmin.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement poison, float %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv8f32( %a, %splat) ret %v } declare @llvm.minnum.nxv16f32(, ) define @vfmin_nxv16f32_vv( %a, %b) { ; CHECK-LABEL: vfmin_nxv16f32_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: ret %v = call @llvm.minnum.nxv16f32( %a, %b) ret %v } define @vfmin_nxv16f32_vf( %a, float %b) { ; CHECK-LABEL: vfmin_nxv16f32_vf: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vfmin.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement poison, float %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv16f32( %a, %splat) ret %v } declare @llvm.minnum.nxv1f64(, ) define @vfmin_nxv1f64_vv( %a, %b) { ; CHECK-LABEL: vfmin_nxv1f64_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.minnum.nxv1f64( %a, %b) ret %v } define @vfmin_nxv1f64_vf( %a, double %b) { ; CHECK-LABEL: vfmin_nxv1f64_vf: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vfmin.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement poison, double %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv1f64( %a, %splat) ret %v } declare @llvm.minnum.nxv2f64(, ) define @vfmin_nxv2f64_vv( %a, %b) { ; CHECK-LABEL: vfmin_nxv2f64_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v10 ; CHECK-NEXT: ret %v = call @llvm.minnum.nxv2f64( %a, %b) ret %v } define @vfmin_nxv2f64_vf( %a, double %b) { ; CHECK-LABEL: vfmin_nxv2f64_vf: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vfmin.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement poison, double %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv2f64( %a, %splat) ret %v } declare @llvm.minnum.nxv4f64(, ) define @vfmin_nxv4f64_vv( %a, %b) { ; CHECK-LABEL: vfmin_nxv4f64_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v12 ; CHECK-NEXT: ret %v = call @llvm.minnum.nxv4f64( %a, %b) ret %v } define @vfmin_nxv4f64_vf( %a, double %b) { ; CHECK-LABEL: vfmin_nxv4f64_vf: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vfmin.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement poison, double %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv4f64( %a, %splat) ret %v } declare @llvm.minnum.nxv8f64(, ) define @vfmin_nxv8f64_vv( %a, %b) { ; CHECK-LABEL: vfmin_nxv8f64_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: ret %v = call @llvm.minnum.nxv8f64( %a, %b) ret %v } define @vfmin_nxv8f64_vf( %a, double %b) { ; CHECK-LABEL: vfmin_nxv8f64_vf: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vfmin.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement poison, double %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %v = call @llvm.minnum.nxv8f64( %a, %splat) ret %v }