; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( , , iXLen); define @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( undef, %0, iXLen %1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16( , , , iXLen, iXLen); define @intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16( %0, %1, %2, iXLen %3, iXLen 1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16( , , iXLen); define @intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16( undef, %0, iXLen %1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16( , , , iXLen, iXLen); define @intrinsic_vfwcvt_mask_f.f.v_nxv2f32_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16( %0, %1, %2, iXLen %3, iXLen 1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16( , , iXLen); define @intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16( undef, %0, iXLen %1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f32.nxv4f16( , , , iXLen, iXLen); define @intrinsic_vfwcvt_mask_f.f.v_nxv4f32_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f32.nxv4f16( %0, %1, %2, iXLen %3, iXLen 1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16( , , iXLen); define @intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfwcvt.f.f.v v12, v8 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16( undef, %0, iXLen %1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f32.nxv8f16( , , , iXLen, iXLen); define @intrinsic_vfwcvt_mask_f.f.v_nxv8f32_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v12, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f32.nxv8f16( %0, %1, %2, iXLen %3, iXLen 1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16( , , iXLen); define @intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfwcvt.f.f.v v16, v8 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16( undef, %0, iXLen %1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv16f32.nxv16f16( , , , iXLen, iXLen); define @intrinsic_vfwcvt_mask_f.f.v_nxv16f32_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v16, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv16f32.nxv16f16( %0, %1, %2, iXLen %3, iXLen 1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32( , , iXLen); define @intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32( undef, %0, iXLen %1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32( , , , iXLen, iXLen); define @intrinsic_vfwcvt_mask_f.f.v_nxv1f64_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32( %0, %1, %2, iXLen %3, iXLen 1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32( , , iXLen); define @intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32( undef, %0, iXLen %1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32( , , , iXLen, iXLen); define @intrinsic_vfwcvt_mask_f.f.v_nxv2f64_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32( %0, %1, %2, iXLen %3, iXLen 1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32( , , iXLen); define @intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfwcvt.f.f.v v12, v8 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32( undef, %0, iXLen %1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32( , , , iXLen, iXLen); define @intrinsic_vfwcvt_mask_f.f.v_nxv4f64_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v12, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32( %0, %1, %2, iXLen %3, iXLen 1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32( , , iXLen); define @intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfwcvt.f.f.v v16, v8 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32( undef, %0, iXLen %1) ret %a } declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32( , , , iXLen, iXLen); define @intrinsic_vfwcvt_mask_f.f.v_nxv8f64_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v16, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32( %0, %1, %2, iXLen %3, iXLen 1) ret %a }