; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; This tests a mix of vmacc and vmadd by using different operand orders to ; trigger commuting in TwoAddressInstructionPass. define @vmadd_vv_nxv1i8( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmadd.vv v8, v9, v10 ; CHECK-NEXT: ret %x = mul %va, %vb %y = add %x, %vc ret %y } define @vmadd_vx_nxv1i8( %va, %vb, i8 %c) { ; CHECK-LABEL: vmadd_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmadd.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement poison, i8 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv2i8( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmadd.vv v8, v10, v9 ; CHECK-NEXT: ret %x = mul %va, %vc %y = add %x, %vb ret %y } define @vmadd_vx_nxv2i8( %va, %vb, i8 %c) { ; CHECK-LABEL: vmadd_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmacc.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement poison, i8 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @vmadd_vv_nxv4i8( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmadd.vv v8, v9, v10 ; CHECK-NEXT: ret %x = mul %vb, %va %y = add %x, %vc ret %y } define @vmadd_vx_nxv4i8( %va, %vb, i8 %c) { ; CHECK-LABEL: vmadd_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmadd.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement poison, i8 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv8i8( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmacc.vv v8, v10, v9 ; CHECK-NEXT: ret %x = mul %vb, %vc %y = add %x, %va ret %y } define @vmadd_vx_nxv8i8( %va, %vb, i8 %c) { ; CHECK-LABEL: vmadd_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmacc.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement poison, i8 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @vmadd_vv_nxv16i8( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vmadd.vv v8, v12, v10 ; CHECK-NEXT: ret %x = mul %vc, %va %y = add %x, %vb ret %y } define @vmadd_vx_nxv16i8( %va, %vb, i8 %c) { ; CHECK-LABEL: vmadd_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vmadd.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement poison, i8 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv32i8( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vmacc.vv v8, v16, v12 ; CHECK-NEXT: ret %x = mul %vc, %vb %y = add %x, %va ret %y } define @vmadd_vx_nxv32i8( %va, %vb, i8 %c) { ; CHECK-LABEL: vmadd_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vmacc.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement poison, i8 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @vmadd_vv_nxv64i8( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vmacc.vv v8, v16, v24 ; CHECK-NEXT: ret %x = mul %vc, %vb %y = add %x, %va ret %y } define @vmadd_vx_nxv64i8( %va, %vb, i8 %c) { ; CHECK-LABEL: vmadd_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vmacc.vx v8, a0, v16 ; CHECK-NEXT: ret %head = insertelement poison, i8 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @vmadd_vv_nxv1i16( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vmadd.vv v8, v9, v10 ; CHECK-NEXT: ret %x = mul %va, %vb %y = add %x, %vc ret %y } define @vmadd_vx_nxv1i16( %va, %vb, i16 %c) { ; CHECK-LABEL: vmadd_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vmadd.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement poison, i16 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv2i16( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vmadd.vv v8, v10, v9 ; CHECK-NEXT: ret %x = mul %va, %vc %y = add %x, %vb ret %y } define @vmadd_vx_nxv2i16( %va, %vb, i16 %c) { ; CHECK-LABEL: vmadd_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vmacc.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement poison, i16 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @vmadd_vv_nxv4i16( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vmadd.vv v8, v9, v10 ; CHECK-NEXT: ret %x = mul %vb, %va %y = add %x, %vc ret %y } define @vmadd_vx_nxv4i16( %va, %vb, i16 %c) { ; CHECK-LABEL: vmadd_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vmadd.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement poison, i16 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv8i16( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmacc.vv v8, v12, v10 ; CHECK-NEXT: ret %x = mul %vb, %vc %y = add %x, %va ret %y } define @vmadd_vx_nxv8i16( %va, %vb, i16 %c) { ; CHECK-LABEL: vmadd_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmacc.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement poison, i16 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @vmadd_vv_nxv16i16( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vmadd.vv v8, v16, v12 ; CHECK-NEXT: ret %x = mul %vc, %va %y = add %x, %vb ret %y } define @vmadd_vx_nxv16i16( %va, %vb, i16 %c) { ; CHECK-LABEL: vmadd_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vmadd.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement poison, i16 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv32i16( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vmacc.vv v8, v16, v24 ; CHECK-NEXT: ret %x = mul %vc, %vb %y = add %x, %va ret %y } define @vmadd_vx_nxv32i16( %va, %vb, i16 %c) { ; CHECK-LABEL: vmadd_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vmacc.vx v8, a0, v16 ; CHECK-NEXT: ret %head = insertelement poison, i16 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @vmadd_vv_nxv1i32( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmadd.vv v8, v9, v10 ; CHECK-NEXT: ret %x = mul %va, %vb %y = add %x, %vc ret %y } define @vmadd_vx_nxv1i32( %va, %vb, i32 %c) { ; CHECK-LABEL: vmadd_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmadd.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement poison, i32 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv2i32( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vmadd.vv v8, v10, v9 ; CHECK-NEXT: ret %x = mul %va, %vc %y = add %x, %vb ret %y } define @vmadd_vx_nxv2i32( %va, %vb, i32 %c) { ; CHECK-LABEL: vmadd_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmacc.vx v8, a0, v9 ; CHECK-NEXT: ret %head = insertelement poison, i32 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @vmadd_vv_nxv4i32( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vmadd.vv v8, v10, v12 ; CHECK-NEXT: ret %x = mul %vb, %va %y = add %x, %vc ret %y } define @vmadd_vx_nxv4i32( %va, %vb, i32 %c) { ; CHECK-LABEL: vmadd_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmadd.vx v8, a0, v10 ; CHECK-NEXT: ret %head = insertelement poison, i32 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv8i32( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmacc.vv v8, v16, v12 ; CHECK-NEXT: ret %x = mul %vb, %vc %y = add %x, %va ret %y } define @vmadd_vx_nxv8i32( %va, %vb, i32 %c) { ; CHECK-LABEL: vmadd_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmacc.vx v8, a0, v12 ; CHECK-NEXT: ret %head = insertelement poison, i32 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @vmadd_vv_nxv16i32( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vmadd.vv v8, v24, v16 ; CHECK-NEXT: ret %x = mul %vc, %va %y = add %x, %vb ret %y } define @vmadd_vx_nxv16i32( %va, %vb, i32 %c) { ; CHECK-LABEL: vmadd_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vmadd.vx v8, a0, v16 ; CHECK-NEXT: ret %head = insertelement poison, i32 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv1i64( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vmadd.vv v8, v9, v10 ; CHECK-NEXT: ret %x = mul %va, %vb %y = add %x, %vc ret %y } define @vmadd_vx_nxv1i64( %va, %vb, i64 %c) { ; RV32-LABEL: vmadd_vx_nxv1i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmadd.vv v8, v10, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vmadd_vx_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vmadd.vx v8, a0, v9 ; RV64-NEXT: ret %head = insertelement poison, i64 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv2i64( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vmadd.vv v8, v12, v10 ; CHECK-NEXT: ret %x = mul %va, %vc %y = add %x, %vb ret %y } define @vmadd_vx_nxv2i64( %va, %vb, i64 %c) { ; RV32-LABEL: vmadd_vx_nxv2i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmacc.vv v8, v10, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vmadd_vx_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV64-NEXT: vmacc.vx v8, a0, v10 ; RV64-NEXT: ret %head = insertelement poison, i64 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @vmadd_vv_nxv4i64( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vmadd.vv v8, v12, v16 ; CHECK-NEXT: ret %x = mul %vb, %va %y = add %x, %vc ret %y } define @vmadd_vx_nxv4i64( %va, %vb, i64 %c) { ; RV32-LABEL: vmadd_vx_nxv4i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmadd.vv v8, v16, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vmadd_vx_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vmadd.vx v8, a0, v12 ; RV64-NEXT: ret %head = insertelement poison, i64 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %va, %splat %y = add %x, %vb ret %y } define @vmadd_vv_nxv8i64( %va, %vb, %vc) { ; CHECK-LABEL: vmadd_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmacc.vv v8, v16, v24 ; CHECK-NEXT: ret %x = mul %vb, %vc %y = add %x, %va ret %y } define @vmadd_vx_nxv8i64( %va, %vb, i64 %c) { ; RV32-LABEL: vmadd_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmacc.vv v8, v16, v24 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vmadd_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmacc.vx v8, a0, v16 ; RV64-NEXT: ret %head = insertelement poison, i64 %c, i32 0 %splat = shufflevector %head, poison, zeroinitializer %x = mul %vb, %splat %y = add %x, %va ret %y } define @combine_mul_add_imm1( %a, %b) { ; CHECK-LABEL: combine_mul_add_imm1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vmadd.vv v8, v10, v10 ; CHECK-NEXT: ret %x = add %a, shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) %y = mul %x, %b ret %y } define @combine_mul_add_imm1_2( %a, %b) { ; CHECK-LABEL: combine_mul_add_imm1_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vmadd.vv v8, v10, v10 ; CHECK-NEXT: ret %x = add %a, shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) %y = mul %b, %x ret %y }