; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vmfle.nxv1f16( , , iXLen); define @intrinsic_vmfle_vv_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv1f16( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv1f16( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv1f16( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv1f16( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv2f16( , , iXLen); define @intrinsic_vmfle_vv_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv2f16( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv2f16( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv2f16( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv2f16( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv4f16( , , iXLen); define @intrinsic_vmfle_vv_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv4f16( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv4f16( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv4f16( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv4f16( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv8f16( , , iXLen); define @intrinsic_vmfle_vv_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv8f16( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv8f16( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmfle.vv v14, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv8f16( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv8f16( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv16f16( , , iXLen); define @intrinsic_vmfle_vv_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv16f16( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv16f16( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmfle.vv v20, v8, v12 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv16f16( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv16f16( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv1f32( , , iXLen); define @intrinsic_vmfle_vv_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv1f32( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv1f32( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv1f32( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv1f32( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv2f32( , , iXLen); define @intrinsic_vmfle_vv_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv2f32( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv2f32( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv2f32( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv2f32( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv4f32( , , iXLen); define @intrinsic_vmfle_vv_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv4f32( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv4f32( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmfle.vv v14, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv4f32( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv4f32( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv8f32( , , iXLen); define @intrinsic_vmfle_vv_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv8f32( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv8f32( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmfle.vv v20, v8, v12 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv8f32( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv8f32( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv1f64( , , iXLen); define @intrinsic_vmfle_vv_nxv1f64_nxv1f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv1f64( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv1f64( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv1f64( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv1f64( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv2f64( , , iXLen); define @intrinsic_vmfle_vv_nxv2f64_nxv2f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv2f64( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv2f64( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmfle.vv v14, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv2f64( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv2f64( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv4f64( , , iXLen); define @intrinsic_vmfle_vv_nxv4f64_nxv4f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv4f64( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv4f64( , , , , iXLen); define @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmfle.vv v20, v8, v12 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv4f64( %1, %2, iXLen %4) %a = call @llvm.riscv.vmfle.mask.nxv4f64( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv1f16.f16( , half, iXLen); define @intrinsic_vmfle_vf_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv1f16.f16( %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv1f16.f16( , , half, , iXLen); define @intrinsic_vmfle_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv1f16.f16( %0, %1, half %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv2f16.f16( , half, iXLen); define @intrinsic_vmfle_vf_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv2f16.f16( %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv2f16.f16( , , half, , iXLen); define @intrinsic_vmfle_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv2f16.f16( %0, %1, half %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv4f16.f16( , half, iXLen); define @intrinsic_vmfle_vf_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv4f16.f16( %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv4f16.f16( , , half, , iXLen); define @intrinsic_vmfle_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv4f16.f16( %0, %1, half %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv8f16.f16( , half, iXLen); define @intrinsic_vmfle_vf_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv8f16.f16( %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv8f16.f16( , , half, , iXLen); define @intrinsic_vmfle_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv8f16.f16( %0, %1, half %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv16f16.f16( , half, iXLen); define @intrinsic_vmfle_vf_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv16f16.f16( %0, half %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv16f16.f16( , , half, , iXLen); define @intrinsic_vmfle_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv16f16.f16( %0, %1, half %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv1f32.f32( , float, iXLen); define @intrinsic_vmfle_vf_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv1f32.f32( %0, float %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv1f32.f32( , , float, , iXLen); define @intrinsic_vmfle_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv1f32.f32( %0, %1, float %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv2f32.f32( , float, iXLen); define @intrinsic_vmfle_vf_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv2f32.f32( %0, float %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv2f32.f32( , , float, , iXLen); define @intrinsic_vmfle_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv2f32.f32( %0, %1, float %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv4f32.f32( , float, iXLen); define @intrinsic_vmfle_vf_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv4f32.f32( %0, float %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv4f32.f32( , , float, , iXLen); define @intrinsic_vmfle_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv4f32.f32( %0, %1, float %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv8f32.f32( , float, iXLen); define @intrinsic_vmfle_vf_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv8f32.f32( %0, float %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv8f32.f32( , , float, , iXLen); define @intrinsic_vmfle_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv8f32.f32( %0, %1, float %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv1f64.f64( , double, iXLen); define @intrinsic_vmfle_vf_nxv1f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv1f64.f64( %0, double %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv1f64.f64( , , double, , iXLen); define @intrinsic_vmfle_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv1f64.f64( %0, %1, double %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv2f64.f64( , double, iXLen); define @intrinsic_vmfle_vf_nxv2f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv2f64.f64( %0, double %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv2f64.f64( , , double, , iXLen); define @intrinsic_vmfle_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv2f64.f64( %0, %1, double %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmfle.nxv4f64.f64( , double, iXLen); define @intrinsic_vmfle_vf_nxv4f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.nxv4f64.f64( %0, double %1, iXLen %2) ret %a } declare @llvm.riscv.vmfle.mask.nxv4f64.f64( , , double, , iXLen); define @intrinsic_vmfle_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmfle.mask.nxv4f64.f64( %0, %1, double %2, %3, iXLen %4) ret %a }