; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ ; RUN: -verify-machineinstrs | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ ; RUN: -verify-machineinstrs | FileCheck %s declare @llvm.riscv.vmnand.nxv1i1( , , iXLen); define @intrinsic_vmnand_mm_nxv1i1( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmnand.nxv1i1( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmnand.nxv2i1( , , iXLen); define @intrinsic_vmnand_mm_nxv2i1( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmnand.nxv2i1( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmnand.nxv4i1( , , iXLen); define @intrinsic_vmnand_mm_nxv4i1( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmnand.nxv4i1( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmnand.nxv8i1( , , iXLen); define @intrinsic_vmnand_mm_nxv8i1( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmnand.nxv8i1( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmnand.nxv16i1( , , iXLen); define @intrinsic_vmnand_mm_nxv16i1( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmnand.nxv16i1( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmnand.nxv32i1( , , iXLen); define @intrinsic_vmnand_mm_nxv32i1( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmnand.nxv32i1( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmnand.nxv64i1( , , iXLen); define @intrinsic_vmnand_mm_nxv64i1( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmnand.nxv64i1( %0, %1, iXLen %2) ret %a }