; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.riscv.vmsgeu.nxv1i8( , , iXLen); define @intrinsic_vmsgeu_vv_nxv1i8_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i8( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv1i8( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv1i8( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv1i8( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv2i8( , , iXLen); define @intrinsic_vmsgeu_vv_nxv2i8_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i8( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv2i8( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv2i8( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv2i8( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv4i8( , , iXLen); define @intrinsic_vmsgeu_vv_nxv4i8_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i8( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv4i8( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv4i8( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv4i8( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv8i8( , , iXLen); define @intrinsic_vmsgeu_vv_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i8( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv8i8( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv8i8( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv8i8( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv16i8( , , iXLen); define @intrinsic_vmsgeu_vv_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv16i8( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv16i8( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv16i8( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv16i8( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv32i8( , , iXLen); define @intrinsic_vmsgeu_vv_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv32i8( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv32i8( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv32i8( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv32i8( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv1i16( , , iXLen); define @intrinsic_vmsgeu_vv_nxv1i16_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i16( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv1i16( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv1i16( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv1i16( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv2i16( , , iXLen); define @intrinsic_vmsgeu_vv_nxv2i16_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i16( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv2i16( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv2i16( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv2i16( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv4i16( , , iXLen); define @intrinsic_vmsgeu_vv_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i16( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv4i16( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv4i16( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv4i16( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv8i16( , , iXLen); define @intrinsic_vmsgeu_vv_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i16( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv8i16( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv8i16( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv8i16( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv16i16( , , iXLen); define @intrinsic_vmsgeu_vv_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv16i16( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv16i16( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv16i16( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv16i16( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv1i32( , , iXLen); define @intrinsic_vmsgeu_vv_nxv1i32_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i32( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv1i32( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv1i32( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv1i32( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv2i32( , , iXLen); define @intrinsic_vmsgeu_vv_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i32( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv2i32( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv2i32( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv2i32( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv4i32( , , iXLen); define @intrinsic_vmsgeu_vv_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i32( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv4i32( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv4i32( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv4i32( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv8i32( , , iXLen); define @intrinsic_vmsgeu_vv_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i32( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv8i32( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv8i32( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv8i32( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv1i64( , , iXLen); define @intrinsic_vmsgeu_vv_nxv1i64_nxv1i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i64( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv1i64( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv1i64( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv1i64( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv2i64( , , iXLen); define @intrinsic_vmsgeu_vv_nxv2i64_nxv2i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i64( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv2i64( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv2i64( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv2i64( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv4i64( , , iXLen); define @intrinsic_vmsgeu_vv_nxv4i64_nxv4i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i64( %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv4i64( , , , , iXLen); define @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv4i64( %1, %2, iXLen %4) %a = call @llvm.riscv.vmsgeu.mask.nxv4i64( %0, %2, %3, %mask, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv1i8.i8( , i8, iXLen); define @intrinsic_vmsgeu_vx_nxv1i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmnot.m v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i8.i8( %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8( , , i8, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %0, %1, i8 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv2i8.i8( , i8, iXLen); define @intrinsic_vmsgeu_vx_nxv2i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmnot.m v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i8.i8( %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8( , , i8, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %0, %1, i8 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv4i8.i8( , i8, iXLen); define @intrinsic_vmsgeu_vx_nxv4i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmnot.m v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i8.i8( %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8( , , i8, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %0, %1, i8 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv8i8.i8( , i8, iXLen); define @intrinsic_vmsgeu_vx_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmnot.m v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i8.i8( %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv8i8.i8( , , i8, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %0, %1, i8 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv16i8.i8( , i8, iXLen); define @intrinsic_vmsgeu_vx_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmnot.m v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv16i8.i8( %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv16i8.i8( , , i8, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %0, %1, i8 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv32i8.i8( , i8, iXLen); define @intrinsic_vmsgeu_vx_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmnot.m v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv32i8.i8( %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv32i8.i8( , , i8, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %0, %1, i8 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv1i16.i16( , i16, iXLen); define @intrinsic_vmsgeu_vx_nxv1i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmnot.m v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i16.i16( %0, i16 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv1i16.i16( , , i16, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %0, %1, i16 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv2i16.i16( , i16, iXLen); define @intrinsic_vmsgeu_vx_nxv2i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmnot.m v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i16.i16( %0, i16 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv2i16.i16( , , i16, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %0, %1, i16 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv4i16.i16( , i16, iXLen); define @intrinsic_vmsgeu_vx_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmnot.m v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i16.i16( %0, i16 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv4i16.i16( , , i16, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %0, %1, i16 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv8i16.i16( , i16, iXLen); define @intrinsic_vmsgeu_vx_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmnot.m v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i16.i16( %0, i16 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv8i16.i16( , , i16, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %0, %1, i16 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv16i16.i16( , i16, iXLen); define @intrinsic_vmsgeu_vx_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmnot.m v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv16i16.i16( %0, i16 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv16i16.i16( , , i16, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %0, %1, i16 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv1i32.i32( , i32, iXLen); define @intrinsic_vmsgeu_vx_nxv1i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmnot.m v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i32.i32( %0, i32 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv1i32.i32( , , i32, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %0, %1, i32 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv2i32.i32( , i32, iXLen); define @intrinsic_vmsgeu_vx_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmnot.m v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i32.i32( %0, i32 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv2i32.i32( , , i32, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %0, %1, i32 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv4i32.i32( , i32, iXLen); define @intrinsic_vmsgeu_vx_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmnot.m v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i32.i32( %0, i32 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv4i32.i32( , , i32, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %0, %1, i32 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv8i32.i32( , i32, iXLen); define @intrinsic_vmsgeu_vx_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmnot.m v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i32.i32( %0, i32 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv8i32.i32( , , i32, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %0, %1, i32 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv1i64.i64( , i64, iXLen); define @intrinsic_vmsgeu_vx_nxv1i64_i64( %0, i64 %1, iXLen %2) nounwind { ; RV32-LABEL: intrinsic_vmsgeu_vx_nxv1i64_i64: ; RV32: # %bb.0: # %entry ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v9, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vmsgeu_vx_nxv1i64_i64: ; RV64: # %bb.0: # %entry ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; RV64-NEXT: vmsltu.vx v8, v8, a0 ; RV64-NEXT: vmnot.m v0, v8 ; RV64-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i64.i64( %0, i64 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv1i64.i64( , , i64, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, iXLen %4) nounwind { ; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64: ; RV32: # %bb.0: # %entry ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vlse64.v v11, (a0), zero ; RV32-NEXT: vmv1r.v v10, v0 ; RV32-NEXT: vmv1r.v v0, v9 ; RV32-NEXT: vmsleu.vv v10, v11, v8, v0.t ; RV32-NEXT: vmv.v.v v0, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64: ; RV64: # %bb.0: # %entry ; RV64-NEXT: vmv1r.v v10, v0 ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; RV64-NEXT: vmv1r.v v0, v9 ; RV64-NEXT: vmsltu.vx v10, v8, a0, v0.t ; RV64-NEXT: vmxor.mm v0, v10, v9 ; RV64-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %0, %1, i64 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv2i64.i64( , i64, iXLen); define @intrinsic_vmsgeu_vx_nxv2i64_i64( %0, i64 %1, iXLen %2) nounwind { ; RV32-LABEL: intrinsic_vmsgeu_vx_nxv2i64_i64: ; RV32: # %bb.0: # %entry ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v10, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vmsgeu_vx_nxv2i64_i64: ; RV64: # %bb.0: # %entry ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; RV64-NEXT: vmsltu.vx v10, v8, a0 ; RV64-NEXT: vmnot.m v0, v10 ; RV64-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i64.i64( %0, i64 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv2i64.i64( , , i64, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, iXLen %4) nounwind { ; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64: ; RV32: # %bb.0: # %entry ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmv1r.v v11, v0 ; RV32-NEXT: vmv1r.v v0, v10 ; RV32-NEXT: vmsleu.vv v11, v12, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v11 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64: ; RV64: # %bb.0: # %entry ; RV64-NEXT: vmv1r.v v11, v0 ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; RV64-NEXT: vmv1r.v v0, v10 ; RV64-NEXT: vmsltu.vx v11, v8, a0, v0.t ; RV64-NEXT: vmxor.mm v0, v11, v10 ; RV64-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %0, %1, i64 %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vmsgeu.nxv4i64.i64( , i64, iXLen); define @intrinsic_vmsgeu_vx_nxv4i64_i64( %0, i64 %1, iXLen %2) nounwind { ; RV32-LABEL: intrinsic_vmsgeu_vx_nxv4i64_i64: ; RV32: # %bb.0: # %entry ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v12, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vmsgeu_vx_nxv4i64_i64: ; RV64: # %bb.0: # %entry ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; RV64-NEXT: vmsltu.vx v12, v8, a0 ; RV64-NEXT: vmnot.m v0, v12 ; RV64-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i64.i64( %0, i64 %1, iXLen %2) ret %a } declare @llvm.riscv.vmsgeu.mask.nxv4i64.i64( , , i64, , iXLen); define @intrinsic_vmsgeu_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, iXLen %4) nounwind { ; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64: ; RV32: # %bb.0: # %entry ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmv1r.v v13, v0 ; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmsleu.vv v13, v16, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v13 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64: ; RV64: # %bb.0: # %entry ; RV64-NEXT: vmv1r.v v13, v0 ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; RV64-NEXT: vmv1r.v v0, v12 ; RV64-NEXT: vmsltu.vx v13, v8, a0, v0.t ; RV64-NEXT: vmxor.mm v0, v13, v12 ; RV64-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %0, %1, i64 %2, %3, iXLen %4) ret %a } define @intrinsic_vmsgeu_vi_nxv1i8_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i8.i8( %0, i8 -15, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv1i8_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsgtu.vi v10, v8, -15, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %0, %1, i8 -14, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv2i8_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -14 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i8.i8( %0, i8 -13, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv2i8_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsgtu.vi v10, v8, -13, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %0, %1, i8 -12, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv4i8_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i8.i8( %0, i8 -11, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv4i8_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsgtu.vi v10, v8, -11, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %0, %1, i8 -10, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv8i8_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i8.i8( %0, i8 -9, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv8i8_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsgtu.vi v10, v8, -9, v0.t ; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %0, %1, i8 -8, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv16i8_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv16i8.i8( %0, i8 -7, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv16i8_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmsgtu.vi v11, v8, -7, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %0, %1, i8 -6, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv32i8_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -6 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv32i8.i8( %0, i8 -5, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv32i8_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmsgtu.vi v13, v8, -5, v0.t ; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %0, %1, i8 -4, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv1i16_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -4 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i16.i16( %0, i16 -3, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv1i16_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsgtu.vi v10, v8, -3, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %0, %1, i16 -2, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv2i16_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -2 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i16.i16( %0, i16 -1, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv2i16_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vmor.mm v0, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %0, %1, i16 0, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %0, %1, i16 0, %0, iXLen %2) ret %a } define @intrinsic_vmsgeu_vi_nxv4i16_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i16.i16( %0, i16 0, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv4i16_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsgtu.vi v10, v8, 0, v0.t ; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %0, %1, i16 1, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv8i16_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i16.i16( %0, i16 2, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv8i16_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmsgtu.vi v11, v8, 2, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %0, %1, i16 3, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv16i16_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 3 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv16i16.i16( %0, i16 4, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv16i16_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmsgtu.vi v13, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %0, %1, i16 5, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv1i32_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i32.i32( %0, i32 6, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv1i32_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsgtu.vi v10, v8, 6, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %0, %1, i32 7, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv2i32_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 7 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i32.i32( %0, i32 8, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv2i32_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsgtu.vi v10, v8, 8, v0.t ; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %0, %1, i32 9, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv4i32_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i32.i32( %0, i32 10, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv4i32_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmsgtu.vi v11, v8, 10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %0, %1, i32 11, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv8i32_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv8i32.i32( %0, i32 12, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv8i32_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmsgtu.vi v13, v8, 12, v0.t ; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %0, %1, i32 13, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv1i64_i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv1i64.i64( %0, i64 14, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv1i64_i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsgtu.vi v10, v8, 14, v0.t ; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %0, %1, i64 15, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv2i64_i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 15 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv2i64.i64( %0, i64 16, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv2i64_i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmsgtu.vi v11, v8, -16, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %0, %1, i64 -15, %2, iXLen %3) ret %a } define @intrinsic_vmsgeu_vi_nxv4i64_i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.nxv4i64.i64( %0, i64 -14, iXLen %1) ret %a } define @intrinsic_vmsgeu_mask_vi_nxv4i64_i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmsgtu.vi v13, v8, -14, v0.t ; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %0, %1, i64 -13, %2, iXLen %3) ret %a } ; Test cases where the mask and maskedoff are the same value. define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8( %0, %1, i8 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %0, %1, i8 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8( %0, %1, i8 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %0, %1, i8 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8( %0, %1, i8 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %0, %1, i8 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8( %0, %1, i8 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %0, %1, i8 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8( %0, %1, i8 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %0, %1, i8 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8( %0, %1, i8 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %0, %1, i8 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16( %0, %1, i16 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %0, %1, i16 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16( %0, %1, i16 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %0, %1, i16 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16( %0, %1, i16 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %0, %1, i16 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16( %0, %1, i16 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %0, %1, i16 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16( %0, %1, i16 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %0, %1, i16 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32( %0, %1, i32 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %0, %1, i32 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32( %0, %1, i32 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %0, %1, i32 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32( %0, %1, i32 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %0, %1, i32 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32( %0, %1, i32 %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %0, %1, i32 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64( %0, %1, i64 %2, iXLen %3) nounwind { ; RV32-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64: ; RV32: # %bb.0: # %entry ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64: ; RV64: # %bb.0: # %entry ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; RV64-NEXT: vmsltu.vx v8, v8, a0 ; RV64-NEXT: vmandn.mm v0, v0, v8 ; RV64-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %0, %1, i64 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64( %0, %1, i64 %2, iXLen %3) nounwind { ; RV32-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64: ; RV32: # %bb.0: # %entry ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmv1r.v v10, v0 ; RV32-NEXT: vmsleu.vv v10, v12, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64: ; RV64: # %bb.0: # %entry ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; RV64-NEXT: vmsltu.vx v10, v8, a0 ; RV64-NEXT: vmandn.mm v0, v0, v10 ; RV64-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %0, %1, i64 %2, %0, iXLen %3) ret %a } define @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64( %0, %1, i64 %2, iXLen %3) nounwind { ; RV32-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64: ; RV32: # %bb.0: # %entry ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmv1r.v v12, v0 ; RV32-NEXT: vmsleu.vv v12, v16, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64: ; RV64: # %bb.0: # %entry ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; RV64-NEXT: vmsltu.vx v12, v8, a0 ; RV64-NEXT: vmandn.mm v0, v0, v12 ; RV64-NEXT: ret entry: %a = call @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %0, %1, i64 %2, %0, iXLen %3) ret %a }