; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ ; RUN: -verify-machineinstrs | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ ; RUN: -verify-machineinstrs | FileCheck %s declare @llvm.riscv.vmsif.nxv1i1( , iXLen); define @intrinsic_vmsif_m_nxv1i1( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv1i1( %0, iXLen %1) ret %a } declare @llvm.riscv.vmsif.mask.nxv1i1( , , , iXLen); define @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv1i1( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vmsif.nxv2i1( , iXLen); define @intrinsic_vmsif_m_nxv2i1( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv2i1( %0, iXLen %1) ret %a } declare @llvm.riscv.vmsif.mask.nxv2i1( , , , iXLen); define @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv2i1( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vmsif.nxv4i1( , iXLen); define @intrinsic_vmsif_m_nxv4i1( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv4i1( %0, iXLen %1) ret %a } declare @llvm.riscv.vmsif.mask.nxv4i1( , , , iXLen); define @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv4i1( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vmsif.nxv8i1( , iXLen); define @intrinsic_vmsif_m_nxv8i1( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv8i1( %0, iXLen %1) ret %a } declare @llvm.riscv.vmsif.mask.nxv8i1( , , , iXLen); define @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv8i1( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vmsif.nxv16i1( , iXLen); define @intrinsic_vmsif_m_nxv16i1( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv16i1( %0, iXLen %1) ret %a } declare @llvm.riscv.vmsif.mask.nxv16i1( , , , iXLen); define @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv16i1( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vmsif.nxv32i1( , iXLen); define @intrinsic_vmsif_m_nxv32i1( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv32i1( %0, iXLen %1) ret %a } declare @llvm.riscv.vmsif.mask.nxv32i1( , , , iXLen); define @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv32i1( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vmsif.nxv64i1( , iXLen); define @intrinsic_vmsif_m_nxv64i1( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vmsif.m v8, v0 ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.nxv64i1( %0, iXLen %1) ret %a } declare @llvm.riscv.vmsif.mask.nxv64i1( , , , iXLen); define @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmsif.mask.nxv64i1( %0, %1, %2, iXLen %3) ret %a }