; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vmulhu_vv_nxv1i32( %va, %vb) { ; CHECK-LABEL: vmulhu_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmulhu.vv v8, v9, v8 ; CHECK-NEXT: ret %vc = zext %vb to %vd = zext %va to %ve = mul %vc, %vd %head = insertelement poison, i64 32, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vf = lshr %ve, %splat %vg = trunc %vf to ret %vg } define @vmulhu_vx_nxv1i32( %va, i32 %x) { ; CHECK-LABEL: vmulhu_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret %head1 = insertelement poison, i32 %x, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vi_nxv1i32_0( %va) { ; CHECK-LABEL: vmulhu_vi_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret %head1 = insertelement poison, i32 -7, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vi_nxv1i32_1( %va) { ; RV32-LABEL: vmulhu_vi_nxv1i32_1: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: vsrl.vi v8, v8, 28 ; RV32-NEXT: ret ; ; RV64-LABEL: vmulhu_vi_nxv1i32_1: ; RV64: # %bb.0: ; RV64-NEXT: li a0, 16 ; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vmulhu.vx v8, v8, a0 ; RV64-NEXT: ret %head1 = insertelement poison, i32 16, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vv_nxv2i32( %va, %vb) { ; CHECK-LABEL: vmulhu_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vmulhu.vv v8, v9, v8 ; CHECK-NEXT: ret %vc = zext %vb to %vd = zext %va to %ve = mul %vc, %vd %head = insertelement poison, i64 32, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vf = lshr %ve, %splat %vg = trunc %vf to ret %vg } define @vmulhu_vx_nxv2i32( %va, i32 %x) { ; CHECK-LABEL: vmulhu_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret %head1 = insertelement poison, i32 %x, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vi_nxv2i32_0( %va) { ; CHECK-LABEL: vmulhu_vi_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret %head1 = insertelement poison, i32 -7, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vi_nxv2i32_1( %va) { ; RV32-LABEL: vmulhu_vi_nxv2i32_1: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; RV32-NEXT: vsrl.vi v8, v8, 28 ; RV32-NEXT: ret ; ; RV64-LABEL: vmulhu_vi_nxv2i32_1: ; RV64: # %bb.0: ; RV64-NEXT: li a0, 16 ; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; RV64-NEXT: vmulhu.vx v8, v8, a0 ; RV64-NEXT: ret %head1 = insertelement poison, i32 16, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vv_nxv4i32( %va, %vb) { ; CHECK-LABEL: vmulhu_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vmulhu.vv v8, v10, v8 ; CHECK-NEXT: ret %vc = zext %vb to %vd = zext %va to %ve = mul %vc, %vd %head = insertelement poison, i64 32, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vf = lshr %ve, %splat %vg = trunc %vf to ret %vg } define @vmulhu_vx_nxv4i32( %va, i32 %x) { ; CHECK-LABEL: vmulhu_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret %head1 = insertelement poison, i32 %x, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vi_nxv4i32_0( %va) { ; CHECK-LABEL: vmulhu_vi_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret %head1 = insertelement poison, i32 -7, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vi_nxv4i32_1( %va) { ; RV32-LABEL: vmulhu_vi_nxv4i32_1: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: vsrl.vi v8, v8, 28 ; RV32-NEXT: ret ; ; RV64-LABEL: vmulhu_vi_nxv4i32_1: ; RV64: # %bb.0: ; RV64-NEXT: li a0, 16 ; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vmulhu.vx v8, v8, a0 ; RV64-NEXT: ret %head1 = insertelement poison, i32 16, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vv_nxv8i32( %va, %vb) { ; CHECK-LABEL: vmulhu_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmulhu.vv v8, v12, v8 ; CHECK-NEXT: ret %vc = zext %vb to %vd = zext %va to %ve = mul %vc, %vd %head = insertelement poison, i64 32, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vf = lshr %ve, %splat %vg = trunc %vf to ret %vg } define @vmulhu_vx_nxv8i32( %va, i32 %x) { ; CHECK-LABEL: vmulhu_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret %head1 = insertelement poison, i32 %x, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vi_nxv8i32_0( %va) { ; CHECK-LABEL: vmulhu_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret %head1 = insertelement poison, i32 -7, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf } define @vmulhu_vi_nxv8i32_1( %va) { ; RV32-LABEL: vmulhu_vi_nxv8i32_1: ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; RV32-NEXT: vsrl.vi v8, v8, 28 ; RV32-NEXT: ret ; ; RV64-LABEL: vmulhu_vi_nxv8i32_1: ; RV64: # %bb.0: ; RV64-NEXT: li a0, 16 ; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; RV64-NEXT: vmulhu.vx v8, v8, a0 ; RV64-NEXT: ret %head1 = insertelement poison, i32 16, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc %head2 = insertelement poison, i64 32, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %ve = lshr %vd, %splat2 %vf = trunc %ve to ret %vf }