; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define @vor_vx_nxv1i8( %va, i8 signext %b) { ; CHECK-LABEL: vor_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i8_0( %va) { ; CHECK-LABEL: vor_vx_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i8 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i8_1( %va) { ; CHECK-LABEL: vor_vx_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i8_2( %va) { ; CHECK-LABEL: vor_vx_nxv1i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i8( %va, i8 signext %b) { ; CHECK-LABEL: vor_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i8_0( %va) { ; CHECK-LABEL: vor_vx_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i8 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i8_1( %va) { ; CHECK-LABEL: vor_vx_nxv2i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i8_2( %va) { ; CHECK-LABEL: vor_vx_nxv2i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i8( %va, i8 signext %b) { ; CHECK-LABEL: vor_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i8_0( %va) { ; CHECK-LABEL: vor_vx_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i8 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i8_1( %va) { ; CHECK-LABEL: vor_vx_nxv4i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i8_2( %va) { ; CHECK-LABEL: vor_vx_nxv4i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i8( %va, i8 signext %b) { ; CHECK-LABEL: vor_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i8_0( %va) { ; CHECK-LABEL: vor_vx_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i8 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i8_1( %va) { ; CHECK-LABEL: vor_vx_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i8_2( %va) { ; CHECK-LABEL: vor_vx_nxv8i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i8( %va, i8 signext %b) { ; CHECK-LABEL: vor_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i8_0( %va) { ; CHECK-LABEL: vor_vx_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i8 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i8_1( %va) { ; CHECK-LABEL: vor_vx_nxv16i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i8_2( %va) { ; CHECK-LABEL: vor_vx_nxv16i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv32i8( %va, i8 signext %b) { ; CHECK-LABEL: vor_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv32i8_0( %va) { ; CHECK-LABEL: vor_vx_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i8 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv32i8_1( %va) { ; CHECK-LABEL: vor_vx_nxv32i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv32i8_2( %va) { ; CHECK-LABEL: vor_vx_nxv32i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv64i8( %va, i8 signext %b) { ; CHECK-LABEL: vor_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv64i8_0( %va) { ; CHECK-LABEL: vor_vx_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i8 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv64i8_1( %va) { ; CHECK-LABEL: vor_vx_nxv64i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i8 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv64i8_2( %va) { ; CHECK-LABEL: vor_vx_nxv64i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i8 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i16( %va, i16 signext %b) { ; CHECK-LABEL: vor_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i16_0( %va) { ; CHECK-LABEL: vor_vx_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i16 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i16_1( %va) { ; CHECK-LABEL: vor_vx_nxv1i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i16_2( %va) { ; CHECK-LABEL: vor_vx_nxv1i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i16( %va, i16 signext %b) { ; CHECK-LABEL: vor_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i16_0( %va) { ; CHECK-LABEL: vor_vx_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i16 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i16_1( %va) { ; CHECK-LABEL: vor_vx_nxv2i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i16_2( %va) { ; CHECK-LABEL: vor_vx_nxv2i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i16( %va, i16 signext %b) { ; CHECK-LABEL: vor_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i16_0( %va) { ; CHECK-LABEL: vor_vx_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i16 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i16_1( %va) { ; CHECK-LABEL: vor_vx_nxv4i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i16_2( %va) { ; CHECK-LABEL: vor_vx_nxv4i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i16( %va, i16 signext %b) { ; CHECK-LABEL: vor_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i16_0( %va) { ; CHECK-LABEL: vor_vx_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i16 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i16_1( %va) { ; CHECK-LABEL: vor_vx_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i16_2( %va) { ; CHECK-LABEL: vor_vx_nxv8i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i16( %va, i16 signext %b) { ; CHECK-LABEL: vor_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i16_0( %va) { ; CHECK-LABEL: vor_vx_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i16 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i16_1( %va) { ; CHECK-LABEL: vor_vx_nxv16i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i16_2( %va) { ; CHECK-LABEL: vor_vx_nxv16i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv32i16( %va, i16 signext %b) { ; CHECK-LABEL: vor_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv32i16_0( %va) { ; CHECK-LABEL: vor_vx_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i16 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv32i16_1( %va) { ; CHECK-LABEL: vor_vx_nxv32i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i16 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv32i16_2( %va) { ; CHECK-LABEL: vor_vx_nxv32i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i16 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i32( %va, i32 signext %b) { ; CHECK-LABEL: vor_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i32_0( %va) { ; CHECK-LABEL: vor_vx_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i32 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i32_1( %va) { ; CHECK-LABEL: vor_vx_nxv1i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i32 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i32_2( %va) { ; CHECK-LABEL: vor_vx_nxv1i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i32( %va, i32 signext %b) { ; CHECK-LABEL: vor_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i32_0( %va) { ; CHECK-LABEL: vor_vx_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i32 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i32_1( %va) { ; CHECK-LABEL: vor_vx_nxv2i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i32 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i32_2( %va) { ; CHECK-LABEL: vor_vx_nxv2i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i32( %va, i32 signext %b) { ; CHECK-LABEL: vor_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i32_0( %va) { ; CHECK-LABEL: vor_vx_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i32 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i32_1( %va) { ; CHECK-LABEL: vor_vx_nxv4i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i32 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i32_2( %va) { ; CHECK-LABEL: vor_vx_nxv4i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i32( %va, i32 signext %b) { ; CHECK-LABEL: vor_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i32_0( %va) { ; CHECK-LABEL: vor_vx_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i32 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i32_1( %va) { ; CHECK-LABEL: vor_vx_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i32 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i32_2( %va) { ; CHECK-LABEL: vor_vx_nxv8i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i32( %va, i32 signext %b) { ; CHECK-LABEL: vor_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i32_0( %va) { ; CHECK-LABEL: vor_vx_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i32 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i32_1( %va) { ; CHECK-LABEL: vor_vx_nxv16i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i32 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv16i32_2( %va) { ; CHECK-LABEL: vor_vx_nxv16i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i32 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i64( %va, i64 %b) { ; RV32-LABEL: vor_vx_nxv1i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vor_vx_nxv1i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vor.vx v8, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i64_0( %va) { ; CHECK-LABEL: vor_vx_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i64 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i64_1( %va) { ; CHECK-LABEL: vor_vx_nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i64 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv1i64_2( %va) { ; CHECK-LABEL: vor_vx_nxv1i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i64( %va, i64 %b) { ; RV32-LABEL: vor_vx_nxv2i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vor_vx_nxv2i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV64-NEXT: vor.vx v8, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i64_0( %va) { ; CHECK-LABEL: vor_vx_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i64 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i64_1( %va) { ; CHECK-LABEL: vor_vx_nxv2i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i64 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv2i64_2( %va) { ; CHECK-LABEL: vor_vx_nxv2i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i64( %va, i64 %b) { ; RV32-LABEL: vor_vx_nxv4i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vor_vx_nxv4i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vor.vx v8, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i64_0( %va) { ; CHECK-LABEL: vor_vx_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i64 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i64_1( %va) { ; CHECK-LABEL: vor_vx_nxv4i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i64 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv4i64_2( %va) { ; CHECK-LABEL: vor_vx_nxv4i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i64( %va, i64 %b) { ; RV32-LABEL: vor_vx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vor_vx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vor.vx v8, v8, a0 ; RV64-NEXT: ret %head = insertelement poison, i64 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i64_0( %va) { ; CHECK-LABEL: vor_vx_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement poison, i64 -12, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i64_1( %va) { ; CHECK-LABEL: vor_vx_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement poison, i64 15, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i64_2( %va) { ; CHECK-LABEL: vor_vx_nxv8i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement poison, i64 16, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_vx_nxv8i64_3( %va) { ; CHECK-LABEL: vor_vx_nxv8i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: ret %head = insertelement poison, i64 -1, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = or %va, %splat ret %vc } define @vor_xx_nxv8i64(i64 %a, i64 %b) nounwind { ; RV32-LABEL: vor_xx_nxv8i64: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v8, (a0), zero ; RV32-NEXT: sw a3, 4(sp) ; RV32-NEXT: sw a2, 0(sp) ; RV32-NEXT: mv a0, sp ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: vor_xx_nxv8i64: ; RV64: # %bb.0: ; RV64-NEXT: or a0, a0, a1 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vmv.v.x v8, a0 ; RV64-NEXT: ret %head1 = insertelement poison, i64 %a, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer %head2 = insertelement poison, i64 %b, i32 0 %splat2 = shufflevector %head2, poison, zeroinitializer %v = or %splat1, %splat2 ret %v } define @vor_vv_mask_nxv8i32( %va, %vb, %mask) { ; CHECK-LABEL: vor_vv_mask_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vor.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret %vs = select %mask, %vb, zeroinitializer %vc = or %va, %vs ret %vc } define @vor_vx_mask_nxv8i32( %va, i32 signext %b, %mask) { ; CHECK-LABEL: vor_vx_mask_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vor.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vs = select %mask, %splat, zeroinitializer %vc = or %va, %vs ret %vc } define @vor_vi_mask_nxv8i32( %va, %mask) { ; CHECK-LABEL: vor_vi_mask_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret %head = insertelement poison, i32 7, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vs = select %mask, %splat, zeroinitializer %vc = or %va, %vs ret %vc }