; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s define @test_vp_reverse_nxv1i64_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv1i64_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vid.v v9, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t ; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv1i64( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv1i64( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: vrsub.vx v10, v9, a1 ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv1i64( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv2i32_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv2i32_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vid.v v9, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t ; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv2i32( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv2i32( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: vrsub.vx v10, v9, a1 ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv2i32( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv4i16_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv4i16_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vid.v v9, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t ; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv4i16( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv4i16( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: vrsub.vx v10, v9, a1 ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv4i16( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv8i8_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv8i8_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vid.v v10, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma ; CHECK-NEXT: vrgatherei16.vv v9, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv8i8( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv8i8( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vrsub.vx v10, v10, a1 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma ; CHECK-NEXT: vrgatherei16.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv8i8( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv2i64_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv2i64_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vid.v v10, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t ; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv2i64( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv2i64( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vrsub.vx v12, v10, a1 ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv2i64( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv4i32_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv4i32_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vid.v v10, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t ; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv4i32( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv4i32( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vrsub.vx v12, v10, a1 ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv4i32( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv8i16_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv8i16_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vid.v v10, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t ; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv8i16( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv8i16( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vrsub.vx v12, v10, a1 ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv8i16( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv16i8_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv16i8_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vid.v v12, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v12, v12, a0, v0.t ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma ; CHECK-NEXT: vrgatherei16.vv v10, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv16i8( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv16i8( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vid.v v12 ; CHECK-NEXT: vrsub.vx v12, v12, a1 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma ; CHECK-NEXT: vrgatherei16.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv16i8( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv4i64_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv4i64_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vid.v v12, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t ; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv4i64( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv4i64( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vid.v v12 ; CHECK-NEXT: vrsub.vx v16, v12, a1 ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv4i64( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv8i32_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv8i32_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vid.v v12, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t ; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv8i32( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv8i32( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vid.v v12 ; CHECK-NEXT: vrsub.vx v16, v12, a1 ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv8i32( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv16i16_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv16i16_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vid.v v12, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t ; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv16i16( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv16i16( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vid.v v12 ; CHECK-NEXT: vrsub.vx v16, v12, a1 ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv16i16( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv32i8_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv32i8_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vid.v v16, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v16, v16, a0, v0.t ; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv32i8( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv32i8( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vid.v v16 ; CHECK-NEXT: vrsub.vx v16, v16, a1 ; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv32i8( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv8i64_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv8i64_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vid.v v16, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t ; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv8i64( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv8i64( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vid.v v16 ; CHECK-NEXT: vrsub.vx v24, v16, a1 ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv8i64( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv16i32_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv16i32_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vid.v v16, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t ; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv16i32( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv16i32( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vid.v v16 ; CHECK-NEXT: vrsub.vx v24, v16, a1 ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv16i32( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv32i16_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv32i16_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vid.v v16, v0.t ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t ; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv32i16( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv32i16( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vid.v v16 ; CHECK-NEXT: vrsub.vx v24, v16, a1 ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv32i16( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv64i8_masked( %src, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv64i8_masked: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: slli a2, a1, 2 ; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: vsetvli a3, zero, e16, m8, ta, ma ; CHECK-NEXT: vid.v v16 ; CHECK-NEXT: vrsub.vx v24, v16, a2 ; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; CHECK-NEXT: vrgatherei16.vv v20, v8, v24 ; CHECK-NEXT: vrgatherei16.vv v16, v12, v24 ; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: sub a1, a1, a0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v16, a1, v0.t ; CHECK-NEXT: ret %dst = call @llvm.experimental.vp.reverse.nxv64i8( %src, %mask, i32 %evl) ret %dst } define @test_vp_reverse_nxv64i8( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: slli a2, a1, 2 ; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: vsetvli a3, zero, e16, m8, ta, ma ; CHECK-NEXT: vid.v v16 ; CHECK-NEXT: vrsub.vx v16, v16, a2 ; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; CHECK-NEXT: vrgatherei16.vv v28, v8, v16 ; CHECK-NEXT: vrgatherei16.vv v24, v12, v16 ; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: sub a1, a1, a0 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v24, a1 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv64i8( %src, %allones, i32 %evl) ret %dst } define @test_vp_reverse_nxv128i8( %src, i32 zeroext %evl) { ; CHECK-LABEL: test_vp_reverse_nxv128i8: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: bltu a0, a1, .LBB32_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: .LBB32_2: ; CHECK-NEXT: addi sp, sp, -80 ; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: addi s0, sp, 80 ; CHECK-NEXT: .cfi_def_cfa s0, 0 ; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: slli a3, a3, 4 ; CHECK-NEXT: sub sp, sp, a3 ; CHECK-NEXT: andi sp, sp, -64 ; CHECK-NEXT: addi a3, sp, 64 ; CHECK-NEXT: add a4, a0, a3 ; CHECK-NEXT: addi a4, a4, -1 ; CHECK-NEXT: li a5, -1 ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vsse8.v v8, (a4), a5 ; CHECK-NEXT: sub a4, a4, a2 ; CHECK-NEXT: sub a6, a0, a1 ; CHECK-NEXT: sltu a0, a0, a6 ; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: and a0, a0, a6 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsse8.v v16, (a4), a5 ; CHECK-NEXT: add a1, a3, a1 ; CHECK-NEXT: vle8.v v16, (a1) ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vle8.v v8, (a3) ; CHECK-NEXT: addi sp, s0, -80 ; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 80 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %allones = shufflevector %head, undef, zeroinitializer %dst = call @llvm.experimental.vp.reverse.nxv128i8( %src, %allones, i32 %evl) ret %dst } ; LMUL = 1 declare @llvm.experimental.vp.reverse.nxv1i64(,,i32) declare @llvm.experimental.vp.reverse.nxv2i32(,,i32) declare @llvm.experimental.vp.reverse.nxv4i16(,,i32) declare @llvm.experimental.vp.reverse.nxv8i8(,,i32) ; LMUL = 2 declare @llvm.experimental.vp.reverse.nxv2i64(,,i32) declare @llvm.experimental.vp.reverse.nxv4i32(,,i32) declare @llvm.experimental.vp.reverse.nxv8i16(,,i32) declare @llvm.experimental.vp.reverse.nxv16i8(,,i32) ; LMUL = 4 declare @llvm.experimental.vp.reverse.nxv4i64(,,i32) declare @llvm.experimental.vp.reverse.nxv8i32(,,i32) declare @llvm.experimental.vp.reverse.nxv16i16(,,i32) declare @llvm.experimental.vp.reverse.nxv32i8(,,i32) ; LMUL = 8 declare @llvm.experimental.vp.reverse.nxv8i64(,,i32) declare @llvm.experimental.vp.reverse.nxv16i32(,,i32) declare @llvm.experimental.vp.reverse.nxv32i16(,,i32) declare @llvm.experimental.vp.reverse.nxv64i8(,,i32) declare @llvm.experimental.vp.reverse.nxv128i8(,,i32)