; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ ; RUN: -verify-machineinstrs | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ ; RUN: -verify-machineinstrs | FileCheck %s declare @llvm.riscv.vredmax.nxv8i8.nxv1i8( , , , iXLen); define @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv8i8.nxv1i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv8i8.nxv2i8( , , , iXLen); define @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv8i8.nxv2i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv8i8.nxv4i8( , , , iXLen); define @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv8i8.nxv4i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv8i8.nxv8i8( , , , iXLen); define @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv8i8.nxv8i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv8i8.nxv16i8( , , , iXLen); define @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv8i8.nxv16i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv8i8.nxv32i8( , , , iXLen); define @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv8i8.nxv32i8( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv4i16.nxv1i16( , , , iXLen); define @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv4i16.nxv1i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv4i16.nxv2i16( , , , iXLen); define @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv4i16.nxv2i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv4i16.nxv4i16( , , , iXLen); define @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv4i16.nxv4i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv4i16.nxv8i16( , , , iXLen); define @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv4i16.nxv8i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv4i16.nxv16i16( , , , iXLen); define @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv4i16.nxv16i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv4i16.nxv32i16( , , , iXLen); define @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vredmax.vs v8, v16, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv4i16.nxv32i16( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv2i32.nxv1i32( , , , iXLen); define @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv2i32.nxv1i32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv2i32.nxv2i32( , , , iXLen); define @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv2i32.nxv2i32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv2i32.nxv4i32( , , , iXLen); define @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv2i32.nxv4i32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv2i32.nxv8i32( , , , iXLen); define @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv2i32.nxv8i32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv2i32.nxv16i32( , , , iXLen); define @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vredmax.vs v8, v16, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv2i32.nxv16i32( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv1i64.nxv1i64( , , , iXLen); define @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv1i64.nxv1i64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv1i64.nxv2i64( , , , iXLen); define @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv1i64.nxv2i64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv1i64.nxv4i64( , , , iXLen); define @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv1i64.nxv4i64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64( %0, %1, %2, %3, iXLen %4) ret %a } declare @llvm.riscv.vredmax.nxv1i64.nxv8i64( , , , iXLen); define @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vredmax.vs v8, v16, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.nxv1i64.nxv8i64( %0, %1, %2, iXLen %3) ret %a } declare @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64( , , , , iXLen); define @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64( %0, %1, %2, %3, iXLen %4) ret %a }