; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.sadd.sat.nxv1i8(, ) define @sadd_nxv1i8_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv1i8_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv1i8( %va, %b) ret %v } define @sadd_nxv1i8_vx( %va, i8 %b) { ; CHECK-LABEL: sadd_nxv1i8_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv1i8( %va, %vb) ret %v } define @sadd_nxv1i8_vi( %va) { ; CHECK-LABEL: sadd_nxv1i8_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv1i8( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv2i8(, ) define @sadd_nxv2i8_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv2i8_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv2i8( %va, %b) ret %v } define @sadd_nxv2i8_vx( %va, i8 %b) { ; CHECK-LABEL: sadd_nxv2i8_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv2i8( %va, %vb) ret %v } define @sadd_nxv2i8_vi( %va) { ; CHECK-LABEL: sadd_nxv2i8_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv2i8( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv4i8(, ) define @sadd_nxv4i8_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv4i8_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv4i8( %va, %b) ret %v } define @sadd_nxv4i8_vx( %va, i8 %b) { ; CHECK-LABEL: sadd_nxv4i8_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv4i8( %va, %vb) ret %v } define @sadd_nxv4i8_vi( %va) { ; CHECK-LABEL: sadd_nxv4i8_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv4i8( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv8i8(, ) define @sadd_nxv8i8_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv8i8_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv8i8( %va, %b) ret %v } define @sadd_nxv8i8_vx( %va, i8 %b) { ; CHECK-LABEL: sadd_nxv8i8_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv8i8( %va, %vb) ret %v } define @sadd_nxv8i8_vi( %va) { ; CHECK-LABEL: sadd_nxv8i8_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv8i8( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv16i8(, ) define @sadd_nxv16i8_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv16i8_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v10 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv16i8( %va, %b) ret %v } define @sadd_nxv16i8_vx( %va, i8 %b) { ; CHECK-LABEL: sadd_nxv16i8_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv16i8( %va, %vb) ret %v } define @sadd_nxv16i8_vi( %va) { ; CHECK-LABEL: sadd_nxv16i8_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv16i8( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv32i8(, ) define @sadd_nxv32i8_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv32i8_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v12 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv32i8( %va, %b) ret %v } define @sadd_nxv32i8_vx( %va, i8 %b) { ; CHECK-LABEL: sadd_nxv32i8_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv32i8( %va, %vb) ret %v } define @sadd_nxv32i8_vi( %va) { ; CHECK-LABEL: sadd_nxv32i8_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv32i8( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv64i8(, ) define @sadd_nxv64i8_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv64i8_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v16 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv64i8( %va, %b) ret %v } define @sadd_nxv64i8_vx( %va, i8 %b) { ; CHECK-LABEL: sadd_nxv64i8_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv64i8( %va, %vb) ret %v } define @sadd_nxv64i8_vi( %va) { ; CHECK-LABEL: sadd_nxv64i8_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv64i8( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv1i16(, ) define @sadd_nxv1i16_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv1i16_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv1i16( %va, %b) ret %v } define @sadd_nxv1i16_vx( %va, i16 %b) { ; CHECK-LABEL: sadd_nxv1i16_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv1i16( %va, %vb) ret %v } define @sadd_nxv1i16_vi( %va) { ; CHECK-LABEL: sadd_nxv1i16_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv1i16( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv2i16(, ) define @sadd_nxv2i16_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv2i16_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv2i16( %va, %b) ret %v } define @sadd_nxv2i16_vx( %va, i16 %b) { ; CHECK-LABEL: sadd_nxv2i16_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv2i16( %va, %vb) ret %v } define @sadd_nxv2i16_vi( %va) { ; CHECK-LABEL: sadd_nxv2i16_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv2i16( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv4i16(, ) define @sadd_nxv4i16_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv4i16_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv4i16( %va, %b) ret %v } define @sadd_nxv4i16_vx( %va, i16 %b) { ; CHECK-LABEL: sadd_nxv4i16_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv4i16( %va, %vb) ret %v } define @sadd_nxv4i16_vi( %va) { ; CHECK-LABEL: sadd_nxv4i16_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv4i16( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv8i16(, ) define @sadd_nxv8i16_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv8i16_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v10 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv8i16( %va, %b) ret %v } define @sadd_nxv8i16_vx( %va, i16 %b) { ; CHECK-LABEL: sadd_nxv8i16_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv8i16( %va, %vb) ret %v } define @sadd_nxv8i16_vi( %va) { ; CHECK-LABEL: sadd_nxv8i16_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv8i16( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv16i16(, ) define @sadd_nxv16i16_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv16i16_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v12 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv16i16( %va, %b) ret %v } define @sadd_nxv16i16_vx( %va, i16 %b) { ; CHECK-LABEL: sadd_nxv16i16_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv16i16( %va, %vb) ret %v } define @sadd_nxv16i16_vi( %va) { ; CHECK-LABEL: sadd_nxv16i16_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv16i16( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv32i16(, ) define @sadd_nxv32i16_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv32i16_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v16 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv32i16( %va, %b) ret %v } define @sadd_nxv32i16_vx( %va, i16 %b) { ; CHECK-LABEL: sadd_nxv32i16_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv32i16( %va, %vb) ret %v } define @sadd_nxv32i16_vi( %va) { ; CHECK-LABEL: sadd_nxv32i16_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv32i16( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv1i32(, ) define @sadd_nxv1i32_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv1i32_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv1i32( %va, %b) ret %v } define @sadd_nxv1i32_vx( %va, i32 %b) { ; CHECK-LABEL: sadd_nxv1i32_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv1i32( %va, %vb) ret %v } define @sadd_nxv1i32_vi( %va) { ; CHECK-LABEL: sadd_nxv1i32_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv1i32( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv2i32(, ) define @sadd_nxv2i32_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv2i32_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv2i32( %va, %b) ret %v } define @sadd_nxv2i32_vx( %va, i32 %b) { ; CHECK-LABEL: sadd_nxv2i32_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv2i32( %va, %vb) ret %v } define @sadd_nxv2i32_vi( %va) { ; CHECK-LABEL: sadd_nxv2i32_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv2i32( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv4i32(, ) define @sadd_nxv4i32_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv4i32_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v10 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv4i32( %va, %b) ret %v } define @sadd_nxv4i32_vx( %va, i32 %b) { ; CHECK-LABEL: sadd_nxv4i32_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv4i32( %va, %vb) ret %v } define @sadd_nxv4i32_vi( %va) { ; CHECK-LABEL: sadd_nxv4i32_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv4i32( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv8i32(, ) define @sadd_nxv8i32_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv8i32_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v12 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv8i32( %va, %b) ret %v } define @sadd_nxv8i32_vx( %va, i32 %b) { ; CHECK-LABEL: sadd_nxv8i32_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv8i32( %va, %vb) ret %v } define @sadd_nxv8i32_vi( %va) { ; CHECK-LABEL: sadd_nxv8i32_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv8i32( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv16i32(, ) define @sadd_nxv16i32_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv16i32_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v16 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv16i32( %va, %b) ret %v } define @sadd_nxv16i32_vx( %va, i32 %b) { ; CHECK-LABEL: sadd_nxv16i32_vx: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vsadd.vx v8, v8, a0 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv16i32( %va, %vb) ret %v } define @sadd_nxv16i32_vi( %va) { ; CHECK-LABEL: sadd_nxv16i32_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv16i32( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv1i64(, ) define @sadd_nxv1i64_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv1i64_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv1i64( %va, %b) ret %v } define @sadd_nxv1i64_vx( %va, i64 %b) { ; RV32-LABEL: sadd_nxv1i64_vx: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: sadd_nxv1i64_vx: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vsadd.vx v8, v8, a0 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv1i64( %va, %vb) ret %v } define @sadd_nxv1i64_vi( %va) { ; CHECK-LABEL: sadd_nxv1i64_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i64 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv1i64( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv2i64(, ) define @sadd_nxv2i64_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv2i64_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v10 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv2i64( %va, %b) ret %v } define @sadd_nxv2i64_vx( %va, i64 %b) { ; RV32-LABEL: sadd_nxv2i64_vx: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: sadd_nxv2i64_vx: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV64-NEXT: vsadd.vx v8, v8, a0 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv2i64( %va, %vb) ret %v } define @sadd_nxv2i64_vi( %va) { ; CHECK-LABEL: sadd_nxv2i64_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i64 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv2i64( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv4i64(, ) define @sadd_nxv4i64_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv4i64_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v12 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv4i64( %va, %b) ret %v } define @sadd_nxv4i64_vx( %va, i64 %b) { ; RV32-LABEL: sadd_nxv4i64_vx: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: sadd_nxv4i64_vx: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vsadd.vx v8, v8, a0 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv4i64( %va, %vb) ret %v } define @sadd_nxv4i64_vi( %va) { ; CHECK-LABEL: sadd_nxv4i64_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i64 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv4i64( %va, %vb) ret %v } declare @llvm.sadd.sat.nxv8i64(, ) define @sadd_nxv8i64_vv( %va, %b) { ; CHECK-LABEL: sadd_nxv8i64_vv: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v16 ; CHECK-NEXT: ret %v = call @llvm.sadd.sat.nxv8i64( %va, %b) ret %v } define @sadd_nxv8i64_vx( %va, i64 %b) { ; RV32-LABEL: sadd_nxv8i64_vx: ; RV32: # %bb.0: ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: sadd_nxv8i64_vx: ; RV64: # %bb.0: ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsadd.vx v8, v8, a0 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv8i64( %va, %vb) ret %v } define @sadd_nxv8i64_vi( %va) { ; CHECK-LABEL: sadd_nxv8i64_vi: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret %elt.head = insertelement poison, i64 5, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer %v = call @llvm.sadd.sat.nxv8i64( %va, %vb) ret %v }