; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVFH ; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVFHMIN ; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVFHMIN define @vfmerge_vv_nxv1f16( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv1f16( %va, half %b, %cond) { ; CHECK-ZVFH-LABEL: vfmerge_fv_nxv1f16: ; CHECK-ZVFH: # %bb.0: ; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-ZVFH-NEXT: ret ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv1f16: ; CHECK-ZVFHMIN: # %bb.0: ; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-ZVFHMIN-NEXT: vfmv.v.f v9, fa5 ; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv2f16( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv2f16( %va, half %b, %cond) { ; CHECK-ZVFH-LABEL: vfmerge_fv_nxv2f16: ; CHECK-ZVFH: # %bb.0: ; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-ZVFH-NEXT: ret ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv2f16: ; CHECK-ZVFHMIN: # %bb.0: ; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-ZVFHMIN-NEXT: vfmv.v.f v9, fa5 ; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv4f16( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv4f16( %va, half %b, %cond) { ; CHECK-ZVFH-LABEL: vfmerge_fv_nxv4f16: ; CHECK-ZVFH: # %bb.0: ; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-ZVFH-NEXT: ret ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv4f16: ; CHECK-ZVFHMIN: # %bb.0: ; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-ZVFHMIN-NEXT: vfmv.v.f v10, fa5 ; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv8f16( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv8f16( %va, half %b, %cond) { ; CHECK-ZVFH-LABEL: vfmerge_fv_nxv8f16: ; CHECK-ZVFH: # %bb.0: ; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-ZVFH-NEXT: ret ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv8f16: ; CHECK-ZVFHMIN: # %bb.0: ; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-ZVFHMIN-NEXT: vfmv.v.f v12, fa5 ; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_zv_nxv8f16( %va, %cond) { ; CHECK-LABEL: vfmerge_zv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: ret %head = insertelement poison, half zeroinitializer, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vmerge_truelhs_nxv8f16_0( %va, %vb) { ; CHECK-LABEL: vmerge_truelhs_nxv8f16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: ret %mhead = insertelement poison, i1 1, i32 0 %mtrue = shufflevector %mhead, poison, zeroinitializer %vc = select %mtrue, %va, %vb ret %vc } define @vmerge_falselhs_nxv8f16_0( %va, %vb) { ; CHECK-LABEL: vmerge_falselhs_nxv8f16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %vc = select zeroinitializer, %va, %vb ret %vc } define @vfmerge_vv_nxv16f16( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv16f16( %va, half %b, %cond) { ; CHECK-ZVFH-LABEL: vfmerge_fv_nxv16f16: ; CHECK-ZVFH: # %bb.0: ; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-ZVFH-NEXT: ret ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv16f16: ; CHECK-ZVFHMIN: # %bb.0: ; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-ZVFHMIN-NEXT: vfmv.v.f v16, fa5 ; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv32f16( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv32f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv32f16( %va, half %b, %cond) { ; CHECK-ZVFH-LABEL: vfmerge_fv_nxv32f16: ; CHECK-ZVFH: # %bb.0: ; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-ZVFH-NEXT: ret ; ; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv32f16: ; CHECK-ZVFHMIN: # %bb.0: ; CHECK-ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 ; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-ZVFHMIN-NEXT: vfmv.v.f v24, fa5 ; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; CHECK-ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24 ; CHECK-ZVFHMIN-NEXT: vmv.v.v v20, v16 ; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-ZVFHMIN-NEXT: ret %head = insertelement poison, half %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv1f32( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv1f32( %va, float %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement poison, float %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv2f32( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv2f32( %va, float %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement poison, float %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv4f32( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv4f32( %va, float %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement poison, float %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv8f32( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv8f32( %va, float %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement poison, float %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_zv_nxv8f32( %va, %cond) { ; CHECK-LABEL: vfmerge_zv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: ret %head = insertelement poison, float zeroinitializer, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv16f32( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv16f32( %va, float %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement poison, float %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv1f64( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv1f64( %va, double %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement poison, double %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv2f64( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv2f64( %va, double %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement poison, double %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv4f64( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv4f64( %va, double %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement poison, double %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_vv_nxv8f64( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc } define @vfmerge_fv_nxv8f64( %va, double %b, %cond) { ; CHECK-LABEL: vfmerge_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement poison, double %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vfmerge_zv_nxv8f64( %va, %cond) { ; CHECK-LABEL: vfmerge_zv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: ret %head = insertelement poison, double zeroinitializer, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = select %cond, %splat, %va ret %vc } define @vselect_combine_regression( %va, %vb) { ; CHECK-LABEL: vselect_combine_regression: ; CHECK: # %bb.0: ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb ; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: vl8re64.v v8, (a1) ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vl8re64.v v8, (a0) ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v24, v16, 0 ; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vmseq.vi v0, v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %cond = icmp eq %va, zeroinitializer %sel = select %cond, %vb, zeroinitializer ret %sel } define void @vselect_legalize_regression( %a, %ma, %mb, * %out) { ; CHECK-LABEL: vselect_legalize_regression: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma ; CHECK-NEXT: vlm.v v24, (a0) ; CHECK-NEXT: vmand.mm v1, v0, v24 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a2, a0, 3 ; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v0, v1, a2 ; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv.v.i v24, 0 ; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0 ; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0 ; CHECK-NEXT: vs8r.v v8, (a1) ; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: vs8r.v v16, (a0) ; CHECK-NEXT: ret %cond = and %ma, %mb %sel = select %cond, %a, zeroinitializer store %sel, * %out ret void }