; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvknhb \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknhb \ ; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK ; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \ ; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s ; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \ ; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s ; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled. declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32( , , , iXLen, iXLen) define @intrinsic_vsha2cl_vv_nxv4i32_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vsha2cl_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsha2ch.vv v8, v10, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32( %0, %1, %2, iXLen %3, iXLen 2) ret %a } declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32( , , , iXLen, iXLen) define @intrinsic_vsha2cl_vv_nxv8i32_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vsha2cl_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsha2ch.vv v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32( %0, %1, %2, iXLen %3, iXLen 2) ret %a } declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32( , , , iXLen, iXLen) define @intrinsic_vsha2cl_vv_nxv16i32_nxv16i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vsha2cl_vv_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma ; CHECK-NEXT: vsha2ch.vv v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32( %0, %1, %2, iXLen %3, iXLen 2) ret %a } declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64( , , , iXLen, iXLen) define @intrinsic_vsha2cl_vv_nxv4i64_nxv4i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vsha2cl_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsha2ch.vv v8, v12, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64( %0, %1, %2, iXLen %3, iXLen 2) ret %a } declare @llvm.riscv.vsha2cl.nxv8i64.nxv8i64( , , , iXLen, iXLen) define @intrinsic_vsha2cl_vv_nxv8i64_nxv8i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vsha2cl_vv_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma ; CHECK-NEXT: vsha2ch.vv v8, v16, v24 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vsha2cl.nxv8i64.nxv8i64( %0, %1, %2, iXLen %3, iXLen 2) ret %a }