; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN ; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare @llvm.vp.sitofp.nxv2f16.nxv2i7(, , i32) define @vsitofp_nxv2f16_nxv2i7( %va, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i7: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; ZVFH-NEXT: vadd.vv v8, v8, v8 ; ZVFH-NEXT: vsra.vi v9, v8, 1 ; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; ZVFH-NEXT: vfwcvt.f.x.v v8, v9, v0.t ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i7: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vadd.vv v8, v8, v8 ; ZVFHMIN-NEXT: vsra.vi v8, v8, 1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vsext.vf2 v9, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v9, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f16.nxv2i7( %va, %m, i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f16.nxv2i8(, , i32) define @vsitofp_nxv2f16_nxv2i8( %va, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i8: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; ZVFH-NEXT: vfwcvt.f.x.v v9, v8, v0.t ; ZVFH-NEXT: vmv1r.v v8, v9 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i8: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vsext.vf2 v9, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v9, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f16.nxv2i8( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f16_nxv2i8_unmasked( %va, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i8_unmasked: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; ZVFH-NEXT: vfwcvt.f.x.v v9, v8 ; ZVFH-NEXT: vmv1r.v v8, v9 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i8_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vsext.vf2 v9, v8 ; ZVFHMIN-NEXT: vfwcvt.f.x.v v10, v9 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f16.nxv2i8( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f16.nxv2i16(, , i32) define @vsitofp_nxv2f16_nxv2i16( %va, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i16: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.f.x.v v8, v8, v0.t ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.x.v v9, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f16.nxv2i16( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f16_nxv2i16_unmasked( %va, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i16_unmasked: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.f.x.v v8, v8 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.x.v v9, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f16.nxv2i16( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f16.nxv2i32(, , i32) define @vsitofp_nxv2f16_nxv2i32( %va, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i32: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFH-NEXT: vfncvt.f.x.w v9, v8, v0.t ; ZVFH-NEXT: vmv1r.v v8, v9 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.f.x.v v9, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f16.nxv2i32( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f16_nxv2i32_unmasked( %va, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i32_unmasked: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFH-NEXT: vfncvt.f.x.w v9, v8 ; ZVFH-NEXT: vmv1r.v v8, v9 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.f.x.v v9, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f16.nxv2i32( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f16.nxv2i64(, , i32) define @vsitofp_nxv2f16_nxv2i64( %va, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i64: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; ZVFH-NEXT: vfncvt.f.x.w v10, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfncvt.f.f.w v8, v10, v0.t ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i64: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.x.w v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f16.nxv2i64( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f16_nxv2i64_unmasked( %va, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i64_unmasked: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; ZVFH-NEXT: vfncvt.f.x.w v10, v8 ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfncvt.f.f.w v8, v10 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vsitofp_nxv2f16_nxv2i64_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.x.w v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f16.nxv2i64( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f32.nxv2i8(, , i32) define @vsitofp_nxv2f32_nxv2i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f32_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsext.vf2 v9, v8, v0.t ; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f32.nxv2i8( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f32_nxv2i8_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f32_nxv2i8_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vfwcvt.f.x.v v8, v9 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f32.nxv2i8( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f32.nxv2i16(, , i32) define @vsitofp_nxv2f32_nxv2i16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f32_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfwcvt.f.x.v v9, v8, v0.t ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f32.nxv2i16( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f32_nxv2i16_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f32_nxv2i16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfwcvt.f.x.v v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f32.nxv2i16( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f32.nxv2i32(, , i32) define @vsitofp_nxv2f32_nxv2i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f32_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f32.nxv2i32( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f32_nxv2i32_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f32_nxv2i32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f32.nxv2i32( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f32.nxv2i64(, , i32) define @vsitofp_nxv2f32_nxv2i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfncvt.f.x.w v10, v8, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f32.nxv2i64( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f32_nxv2i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f32_nxv2i64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfncvt.f.x.w v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f32.nxv2i64( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f64.nxv2i8(, , i32) define @vsitofp_nxv2f64_nxv2i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f64_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsext.vf4 v10, v8, v0.t ; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f64.nxv2i8( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f64_nxv2i8_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f64_nxv2i8_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsext.vf4 v10, v8 ; CHECK-NEXT: vfwcvt.f.x.v v8, v10 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f64.nxv2i8( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f64.nxv2i16(, , i32) define @vsitofp_nxv2f64_nxv2i16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f64_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsext.vf2 v10, v8, v0.t ; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f64.nxv2i16( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f64_nxv2i16_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f64_nxv2i16_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsext.vf2 v10, v8 ; CHECK-NEXT: vfwcvt.f.x.v v8, v10 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f64.nxv2i16( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f64.nxv2i32(, , i32) define @vsitofp_nxv2f64_nxv2i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f64_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfwcvt.f.x.v v10, v8, v0.t ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f64.nxv2i32( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f64_nxv2i32_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f64_nxv2i32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfwcvt.f.x.v v10, v8 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f64.nxv2i32( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv2f64.nxv2i64(, , i32) define @vsitofp_nxv2f64_nxv2i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f64_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f64.nxv2i64( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv2f64_nxv2i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2f64_nxv2i64_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv2f64.nxv2i64( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv32f16.nxv32i32(, , i32) define @vsitofp_nxv32f16_nxv32i32( %va, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv32f16_nxv32i32: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vmv1r.v v24, v0 ; ZVFH-NEXT: csrr a1, vlenb ; ZVFH-NEXT: srli a2, a1, 2 ; ZVFH-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; ZVFH-NEXT: vslidedown.vx v0, v0, a2 ; ZVFH-NEXT: slli a1, a1, 1 ; ZVFH-NEXT: sub a2, a0, a1 ; ZVFH-NEXT: sltu a3, a0, a2 ; ZVFH-NEXT: addi a3, a3, -1 ; ZVFH-NEXT: and a2, a3, a2 ; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma ; ZVFH-NEXT: vfncvt.f.x.w v28, v16, v0.t ; ZVFH-NEXT: bltu a0, a1, .LBB25_2 ; ZVFH-NEXT: # %bb.1: ; ZVFH-NEXT: mv a0, a1 ; ZVFH-NEXT: .LBB25_2: ; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v24 ; ZVFH-NEXT: vfncvt.f.x.w v24, v8, v0.t ; ZVFH-NEXT: vmv8r.v v8, v24 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vsitofp_nxv32f16_nxv32i32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: vmv1r.v v1, v0 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: srli a2, a1, 2 ; ZVFHMIN-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: slli a1, a1, 1 ; ZVFHMIN-NEXT: sub a2, a0, a1 ; ZVFHMIN-NEXT: sltu a3, a0, a2 ; ZVFHMIN-NEXT: addi a3, a3, -1 ; ZVFHMIN-NEXT: and a2, a3, a2 ; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24 ; ZVFHMIN-NEXT: bltu a0, a1, .LBB25_2 ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB25_2: ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v1 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v8 ; ZVFHMIN-NEXT: vmv8r.v v8, v16 ; ZVFHMIN-NEXT: ret %v = call @llvm.vp.sitofp.nxv32f16.nxv32i32( %va, %m, i32 %evl) ret %v } declare @llvm.vp.sitofp.nxv32f32.nxv32i32(, , i32) define @vsitofp_nxv32f32_nxv32i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv32f32_nxv32i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: srli a2, a1, 2 ; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v0, v0, a2 ; CHECK-NEXT: slli a1, a1, 1 ; CHECK-NEXT: sub a2, a0, a1 ; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: and a2, a3, a2 ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t ; CHECK-NEXT: bltu a0, a1, .LBB26_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: .LBB26_2: ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv32f32.nxv32i32( %va, %m, i32 %evl) ret %v } define @vsitofp_nxv32f32_nxv32i32_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv32f32_nxv32i32_unmasked: ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: slli a1, a1, 1 ; CHECK-NEXT: sub a2, a0, a1 ; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: and a2, a3, a2 ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: bltu a0, a1, .LBB27_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: .LBB27_2: ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret %v = call @llvm.vp.sitofp.nxv32f32.nxv32i32( %va, shufflevector ( insertelement ( undef, i1 true, i32 0), undef, zeroinitializer), i32 %evl) ret %v }