; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v,+f -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vslide1up.nxv1i8.i8( , , i8, i32); define @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vslide1up.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv1i8.i8( undef, %0, i8 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv1i8.i8( , , i8, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv1i8.i8( %0, %1, i8 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv2i8.i8( , , i8, i32); define @intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vslide1up.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv2i8.i8( undef, %0, i8 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv2i8.i8( , , i8, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv2i8.i8( %0, %1, i8 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv4i8.i8( , , i8, i32); define @intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vslide1up.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv4i8.i8( undef, %0, i8 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv4i8.i8( , , i8, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv4i8.i8( %0, %1, i8 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv8i8.i8( , , i8, i32); define @intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vslide1up.vx v9, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv8i8.i8( undef, %0, i8 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv8i8.i8( , , i8, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv8i8.i8( %0, %1, i8 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv16i8.i8( , , i8, i32); define @intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vslide1up.vx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv16i8.i8( undef, %0, i8 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv16i8.i8( , , i8, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv16i8.i8( %0, %1, i8 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv32i8.i8( , , i8, i32); define @intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vslide1up.vx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv32i8.i8( undef, %0, i8 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv32i8.i8( , , i8, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv32i8.i8( %0, %1, i8 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv64i8.i8( , , i8, i32); define @intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vslide1up.vx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv64i8.i8( undef, %0, i8 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv64i8.i8( , , i8, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv64i8.i8( %0, %1, i8 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv1i16.i16( , , i16, i32); define @intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vslide1up.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv1i16.i16( undef, %0, i16 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv1i16.i16( , , i16, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv1i16.i16( %0, %1, i16 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv2i16.i16( , , i16, i32); define @intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vslide1up.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv2i16.i16( undef, %0, i16 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv2i16.i16( , , i16, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv2i16.i16( %0, %1, i16 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv4i16.i16( , , i16, i32); define @intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vslide1up.vx v9, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv4i16.i16( undef, %0, i16 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv4i16.i16( , , i16, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv4i16.i16( %0, %1, i16 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv8i16.i16( , , i16, i32); define @intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vslide1up.vx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv8i16.i16( undef, %0, i16 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv8i16.i16( , , i16, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv8i16.i16( %0, %1, i16 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv16i16.i16( , , i16, i32); define @intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vslide1up.vx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv16i16.i16( undef, %0, i16 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv16i16.i16( , , i16, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv16i16.i16( %0, %1, i16 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv32i16.i16( , , i16, i32); define @intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vslide1up.vx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv32i16.i16( undef, %0, i16 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv32i16.i16( , , i16, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv32i16.i16( %0, %1, i16 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv1i32.i32( , , i32, i32); define @intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vslide1up.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv1i32.i32( undef, %0, i32 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv1i32.i32( , , i32, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv1i32.i32( %0, %1, i32 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv2i32.i32( , , i32, i32); define @intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vslide1up.vx v9, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv2i32.i32( undef, %0, i32 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv2i32.i32( , , i32, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv2i32.i32( %0, %1, i32 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv4i32.i32( , , i32, i32); define @intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vslide1up.vx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv4i32.i32( undef, %0, i32 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv4i32.i32( , , i32, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv4i32.i32( %0, %1, i32 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv8i32.i32( , , i32, i32); define @intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vslide1up.vx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv8i32.i32( undef, %0, i32 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv8i32.i32( , , i32, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv8i32.i32( %0, %1, i32 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv16i32.i32( , , i32, i32); define @intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vslide1up.vx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv16i32.i32( undef, %0, i32 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv16i32.i32( , , i32, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vslide1up.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv16i32.i32( %0, %1, i32 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv1i64.i64( , , i64, i32); define @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64, m1, ta, ma ; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-NEXT: vslide1up.vx v9, v8, a1 ; CHECK-NEXT: vslide1up.vx v8, v9, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv1i64.i64( undef, %0, i64 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv1i64.i64( , , i64, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64, m1, ta, ma ; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: vsetvli zero, a3, e32, m1, ta, ma ; CHECK-NEXT: vslide1up.vx v10, v9, a1 ; CHECK-NEXT: vslide1up.vx v9, v10, a0 ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv1i64.i64( %0, %1, i64 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv2i64.i64( , , i64, i32); define @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64, m2, ta, ma ; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma ; CHECK-NEXT: vslide1up.vx v10, v8, a1 ; CHECK-NEXT: vslide1up.vx v8, v10, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv2i64.i64( undef, %0, i64 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv2i64.i64( , , i64, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64, m2, ta, ma ; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, ma ; CHECK-NEXT: vslide1up.vx v12, v10, a1 ; CHECK-NEXT: vslide1up.vx v10, v12, a0 ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv2i64.i64( %0, %1, i64 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv4i64.i64( , , i64, i32); define @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64, m4, ta, ma ; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma ; CHECK-NEXT: vslide1up.vx v12, v8, a1 ; CHECK-NEXT: vslide1up.vx v8, v12, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv4i64.i64( undef, %0, i64 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv4i64.i64( , , i64, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64, m4, ta, ma ; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, ma ; CHECK-NEXT: vslide1up.vx v16, v12, a1 ; CHECK-NEXT: vslide1up.vx v12, v16, a0 ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv4i64.i64( %0, %1, i64 %2, %3, i32 %4, i32 1) ret %a } declare @llvm.riscv.vslide1up.nxv8i64.i64( , , i64, i32); define @intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64, m8, ta, ma ; CHECK-NEXT: slli a2, a2, 1 ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vslide1up.vx v16, v8, a1 ; CHECK-NEXT: vslide1up.vx v8, v16, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.nxv8i64.i64( undef, %0, i64 %1, i32 %2) ret %a } declare @llvm.riscv.vslide1up.mask.nxv8i64.i64( , , i64, , i32, i32); define @intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64, m8, ta, ma ; CHECK-NEXT: slli a3, a3, 1 ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; CHECK-NEXT: vslide1up.vx v24, v16, a1 ; CHECK-NEXT: vslide1up.vx v16, v24, a0 ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vslide1up.mask.nxv8i64.i64( %0, %1, i64 %2, %3, i32 %4, i32 1) ret %a }