; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d \ ; RUN: -verify-machineinstrs | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d \ ; RUN: -verify-machineinstrs | FileCheck %s declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv16i16.nxv16i8( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv16i16.nxv16i8( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv32i16.nxv32i8( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv32i16.nxv32i8( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv1i32.nxv1i16( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv1i32.nxv1i16( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv2i32.nxv2i16( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv2i32.nxv2i16( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv4i32.nxv4i16( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv4i32.nxv4i16( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv8i32.nxv8i16( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv8i32.nxv8i16( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv16i32.nxv16i16( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv16i32.nxv16i16( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv1i64.nxv1i32( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv1i64.nxv1i32( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv2i64.nxv2i32( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv2i64.nxv2i32( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv4i64.nxv4i32( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv4i64.nxv4i32( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv8i64.nxv8i32( , , , iXLen, iXLen); define @intrinsic_vwmaccu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv8i64.nxv8i32( %0, %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32( , , , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32( %0, %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv1i16.i8( , i8, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv1i16_i8_nxv1i8( %0, i8 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv1i16.i8( %0, i8 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv1i16.i8( , i8, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i16.i8( %0, i8 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv2i16.i8( , i8, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv2i16_i8_nxv2i8( %0, i8 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv2i16.i8( %0, i8 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv2i16.i8( , i8, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i16.i8( %0, i8 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv4i16.i8( , i8, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv4i16_i8_nxv4i8( %0, i8 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv4i16.i8( %0, i8 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv4i16.i8( , i8, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i16.i8( %0, i8 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv8i16.i8( , i8, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv8i16_i8_nxv8i8( %0, i8 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv8i16.i8( %0, i8 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv8i16.i8( , i8, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i16.i8( %0, i8 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv16i16.i8( , i8, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv16i16_i8_nxv16i8( %0, i8 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv16i16.i8( %0, i8 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv16i16.i8( , i8, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i16.i8( %0, i8 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv32i16.i8( , i8, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv32i16.i8( %0, i8 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv32i16.i8( , i8, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv32i16.i8( %0, i8 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv1i32.i16( , i16, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv1i32_i16_nxv1i16( %0, i16 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv1i32.i16( %0, i16 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv1i32.i16( , i16, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16( %0, i16 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i32.i16( %0, i16 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv2i32.i16( , i16, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv2i32_i16_nxv2i16( %0, i16 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv2i32.i16( %0, i16 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv2i32.i16( , i16, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16( %0, i16 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i32.i16( %0, i16 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv4i32.i16( , i16, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv4i32_i16_nxv4i16( %0, i16 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv4i32.i16( %0, i16 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv4i32.i16( , i16, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16( %0, i16 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i32.i16( %0, i16 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv8i32.i16( , i16, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv8i32_i16_nxv8i16( %0, i16 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv8i32.i16( %0, i16 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv8i32.i16( , i16, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16( %0, i16 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i32.i16( %0, i16 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv16i32.i16( , i16, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv16i32.i16( %0, i16 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv16i32.i16( , i16, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i32.i16( %0, i16 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv1i64.i32( , i32, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv1i64_i32_nxv1i32( %0, i32 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i64_i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv1i64.i32( %0, i32 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv1i64.i32( , i32, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32( %0, i32 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i64.i32( %0, i32 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv2i64.i32( , i32, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv2i64_i32_nxv2i32( %0, i32 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i64_i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv2i64.i32( %0, i32 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv2i64.i32( , i32, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32( %0, i32 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i64.i32( %0, i32 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv4i64.i32( , i32, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv4i64_i32_nxv4i32( %0, i32 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i64_i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv4i64.i32( %0, i32 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv4i64.i32( , i32, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32( %0, i32 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i64.i32( %0, i32 %1, %2, %3, iXLen %4, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.nxv8i64.i32( , i32, , iXLen, iXLen); define @intrinsic_vwmaccu_vx_nxv8i64_i32_nxv8i32( %0, i32 %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i64_i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma ; CHECK-NEXT: vwmaccu.vx v8, a0, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.nxv8i64.i32( %0, i32 %1, %2, iXLen %3, iXLen 0) ret %a } declare @llvm.riscv.vwmaccu.mask.nxv8i64.i32( , i32, , , iXLen, iXLen); define @intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32( %0, i32 %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i64.i32( %0, i32 %1, %2, %3, iXLen %4, iXLen 0) ret %a }