; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s define @vwmul_vv_nxv1i64( %va, %vb) { ; CHECK-LABEL: vwmul_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %vc = sext %va to %vd = sext %vb to %ve = mul %vc, %vd ret %ve } define @vwmulu_vv_nxv1i64( %va, %vb) { ; CHECK-LABEL: vwmulu_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vwmulu.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %vc = zext %va to %vd = zext %vb to %ve = mul %vc, %vd ret %ve } define @vwmulsu_vv_nxv1i64( %va, %vb) { ; CHECK-LABEL: vwmulsu_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vwmulsu.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %vc = sext %va to %vd = zext %vb to %ve = mul %vc, %vd ret %ve } define @vwmul_vx_nxv1i64( %va, i32 %b) { ; CHECK-LABEL: vwmul_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vwmul.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = sext %va to %vd = sext %splat to %ve = mul %vc, %vd ret %ve } define @vwmulu_vx_nxv1i64( %va, i32 %b) { ; CHECK-LABEL: vwmulu_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vwmulu.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = zext %va to %vd = zext %splat to %ve = mul %vc, %vd ret %ve } define @vwmulsu_vx_nxv1i64( %va, i32 %b) { ; CHECK-LABEL: vwmulsu_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vwmulsu.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = sext %va to %vd = zext %splat to %ve = mul %vc, %vd ret %ve } define @vwmul_vv_nxv2i64( %va, %vb) { ; CHECK-LABEL: vwmul_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %vc = sext %va to %vd = sext %vb to %ve = mul %vc, %vd ret %ve } define @vwmulu_vv_nxv2i64( %va, %vb) { ; CHECK-LABEL: vwmulu_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vwmulu.vv v10, v8, v9 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %vc = zext %va to %vd = zext %vb to %ve = mul %vc, %vd ret %ve } define @vwmulsu_vv_nxv2i64( %va, %vb) { ; CHECK-LABEL: vwmulsu_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vwmulsu.vv v10, v8, v9 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %vc = sext %va to %vd = zext %vb to %ve = mul %vc, %vd ret %ve } define @vwmul_vx_nxv2i64( %va, i32 %b) { ; CHECK-LABEL: vwmul_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vwmul.vx v10, v8, a0 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = sext %va to %vd = sext %splat to %ve = mul %vc, %vd ret %ve } define @vwmulu_vx_nxv2i64( %va, i32 %b) { ; CHECK-LABEL: vwmulu_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vwmulu.vx v10, v8, a0 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = zext %va to %vd = zext %splat to %ve = mul %vc, %vd ret %ve } define @vwmulsu_vx_nxv2i64( %va, i32 %b) { ; CHECK-LABEL: vwmulsu_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vwmulsu.vx v10, v8, a0 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = sext %va to %vd = zext %splat to %ve = mul %vc, %vd ret %ve } define @vwmul_vv_nxv4i64( %va, %vb) { ; CHECK-LABEL: vwmul_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vwmul.vv v12, v8, v10 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %vc = sext %va to %vd = sext %vb to %ve = mul %vc, %vd ret %ve } define @vwmulu_vv_nxv4i64( %va, %vb) { ; CHECK-LABEL: vwmulu_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vwmulu.vv v12, v8, v10 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %vc = zext %va to %vd = zext %vb to %ve = mul %vc, %vd ret %ve } define @vwmulsu_vv_nxv4i64( %va, %vb) { ; CHECK-LABEL: vwmulsu_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vwmulsu.vv v12, v8, v10 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %vc = sext %va to %vd = zext %vb to %ve = mul %vc, %vd ret %ve } define @vwmul_vx_nxv4i64( %va, i32 %b) { ; CHECK-LABEL: vwmul_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vwmul.vx v12, v8, a0 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = sext %va to %vd = sext %splat to %ve = mul %vc, %vd ret %ve } define @vwmulu_vx_nxv4i64( %va, i32 %b) { ; CHECK-LABEL: vwmulu_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vwmulu.vx v12, v8, a0 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = zext %va to %vd = zext %splat to %ve = mul %vc, %vd ret %ve } define @vwmulsu_vx_nxv4i64( %va, i32 %b) { ; CHECK-LABEL: vwmulsu_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vwmulsu.vx v12, v8, a0 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = sext %va to %vd = zext %splat to %ve = mul %vc, %vd ret %ve } define @vwmul_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vwmul_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vwmul.vv v16, v8, v12 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %vc = sext %va to %vd = sext %vb to %ve = mul %vc, %vd ret %ve } define @vwmulu_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vwmulu_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vwmulu.vv v16, v8, v12 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %vc = zext %va to %vd = zext %vb to %ve = mul %vc, %vd ret %ve } define @vwmulsu_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vwmulsu_vv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vwmulsu.vv v16, v8, v12 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %vc = sext %va to %vd = zext %vb to %ve = mul %vc, %vd ret %ve } define @vwmul_vx_nxv8i64( %va, i32 %b) { ; CHECK-LABEL: vwmul_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vwmul.vx v16, v8, a0 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = sext %va to %vd = sext %splat to %ve = mul %vc, %vd ret %ve } define @vwmulu_vx_nxv8i64( %va, i32 %b) { ; CHECK-LABEL: vwmulu_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vwmulu.vx v16, v8, a0 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = zext %va to %vd = zext %splat to %ve = mul %vc, %vd ret %ve } define @vwmulsu_vx_nxv8i64( %va, i32 %b) { ; CHECK-LABEL: vwmulsu_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vwmulsu.vx v16, v8, a0 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer %vc = sext %va to %vd = zext %splat to %ve = mul %vc, %vd ret %ve }