; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ ; RUN: -verify-machineinstrs | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ ; RUN: -verify-machineinstrs | FileCheck %s declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8( , , , iXLen); define @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.nxv1i8( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8( , , , iXLen); define @intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.nxv2i8( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8( , , , iXLen); define @intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.nxv4i8( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8( , , , iXLen); define @intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.nxv8i8( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8( , , , iXLen); define @intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vwmul.vv v12, v8, v10 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.nxv16i8( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv32i16.nxv32i8.nxv32i8( , , , iXLen); define @intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vwmul.vv v16, v8, v12 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv32i16.nxv32i8.nxv32i8( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.nxv32i8( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16( , , , iXLen); define @intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.nxv1i16( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16( , , , iXLen); define @intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.nxv2i16( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16( , , , iXLen); define @intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.nxv4i16( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16( , , , iXLen); define @intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vwmul.vv v12, v8, v10 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.nxv8i16( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv16i32.nxv16i16.nxv16i16( , , , iXLen); define @intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vwmul.vv v16, v8, v12 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv16i32.nxv16i16.nxv16i16( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.nxv16i16( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32( , , , iXLen); define @intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.nxv1i32( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.nxv1i32( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32( , , , iXLen); define @intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vwmul.vv v10, v8, v9 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.nxv2i32( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.nxv2i32( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32( , , , iXLen); define @intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vwmul.vv v12, v8, v10 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.nxv4i32( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.nxv4i32( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv8i64.nxv8i32.nxv8i32( , , , iXLen); define @intrinsic_vwmul_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vwmul.vv v16, v8, v12 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv8i64.nxv8i32.nxv8i32( undef, %0, %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.nxv8i32( , , , , iXLen, iXLen); define @intrinsic_vwmul_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.nxv8i32( %0, %1, %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8( , , i8, iXLen); define @intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vwmul.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8( undef, %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.i8( , , i8, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.i8( %0, %1, i8 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8( , , i8, iXLen); define @intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vwmul.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8( undef, %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.i8( , , i8, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.i8( %0, %1, i8 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8( , , i8, iXLen); define @intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vwmul.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8( undef, %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.i8( , , i8, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.i8( %0, %1, i8 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8( , , i8, iXLen); define @intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vwmul.vx v10, v8, a0 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8( undef, %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.i8( , , i8, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.i8( %0, %1, i8 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8( , , i8, iXLen); define @intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vwmul.vx v12, v8, a0 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8( undef, %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.i8( , , i8, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.i8( %0, %1, i8 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv32i16.nxv32i8.i8( , , i8, iXLen); define @intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vwmul.vx v16, v8, a0 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv32i16.nxv32i8.i8( undef, %0, i8 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.i8( , , i8, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.i8( %0, %1, i8 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16( , , i16, iXLen); define @intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vwmul.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16( undef, %0, i16 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.i16( , , i16, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.i16( %0, %1, i16 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16( , , i16, iXLen); define @intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vwmul.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16( undef, %0, i16 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.i16( , , i16, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.i16( %0, %1, i16 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16( , , i16, iXLen); define @intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vwmul.vx v10, v8, a0 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16( undef, %0, i16 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.i16( , , i16, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.i16( %0, %1, i16 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16( , , i16, iXLen); define @intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vwmul.vx v12, v8, a0 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16( undef, %0, i16 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.i16( , , i16, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.i16( %0, %1, i16 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv16i32.nxv16i16.i16( , , i16, iXLen); define @intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vwmul.vx v16, v8, a0 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv16i32.nxv16i16.i16( undef, %0, i16 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.i16( , , i16, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.i16( %0, %1, i16 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32( , , i32, iXLen); define @intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vwmul.vx v9, v8, a0 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32( undef, %0, i32 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.i32( , , i32, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i64_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.i32( %0, %1, i32 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32( , , i32, iXLen); define @intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vwmul.vx v10, v8, a0 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32( undef, %0, i32 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.i32( , , i32, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i64_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.i32( %0, %1, i32 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32( , , i32, iXLen); define @intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vwmul.vx v12, v8, a0 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32( undef, %0, i32 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.i32( , , i32, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i64_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.i32( %0, %1, i32 %2, %3, iXLen %4, iXLen 1) ret %a } declare @llvm.riscv.vwmul.nxv8i64.nxv8i32.i32( , , i32, iXLen); define @intrinsic_vwmul_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i64_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vwmul.vx v16, v8, a0 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.nxv8i64.nxv8i32.i32( undef, %0, i32 %1, iXLen %2) ret %a } declare @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.i32( , , i32, , iXLen, iXLen); define @intrinsic_vwmul_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i64_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.i32( %0, %1, i32 %2, %3, iXLen %4, iXLen 1) ret %a }