; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s define void @PR57402() { ; CHECK-LABEL: PR57402: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: notl %eax ; CHECK-NEXT: andl $-2, %eax ; CHECK-NEXT: leal 1(%rax,%rax,2), %ecx ; CHECK-NEXT: movswq %cx, %rsi ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: movq $-1, %rax ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: divq %rsi ; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: jne .LBB0_4 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: jne .LBB0_4 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: andl %ecx, %edx ; CHECK-NEXT: movswl %dx, %eax ; CHECK-NEXT: imull %eax, %eax ; CHECK-NEXT: testq %rax, %rax ; CHECK-NEXT: jne .LBB0_3 ; CHECK-NEXT: .LBB0_4: # %if.end ; CHECK-NEXT: retq ; CHECK-NEXT: .LBB0_3: # %if.then entry: %.fr = freeze i64 undef %0 = trunc i64 %.fr to i16 %1 = and i16 %0, -2 %2 = xor i16 %1, -2 %3 = mul i16 %2, 3 %conv = or i16 %3, 1 %conv2 = sext i16 %conv to i64 %rem = urem i64 -1, %conv2 %conv3 = trunc i64 %rem to i32 %sext = shl i32 %conv3, 16 %conv4 = ashr exact i32 %sext, 16 %conv5 = sext i16 %conv to i32 %and = and i32 %conv4, %conv5 %and.fr = freeze i32 %and %conv6 = sext i32 %and.fr to i64 %mul7 = mul i64 %.fr, %conv6 %4 = and i64 %mul7, 4294967295 %tobool1216 = icmp ne i64 %4, 0 %tobool12 = and i1 undef, %tobool1216 %or.cond = and i1 undef, %tobool12 br i1 %or.cond, label %if.then, label %if.end if.then: ; preds = %entry unreachable if.end: ; preds = %entry ret void }