; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s

define <4 x i32> @test_int_x86_vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: test_int_x86_vsm3msg1:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsm3msg1 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x70,0xda,0xc2]
; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
  %ret = call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
  ret <4 x i32> %ret
}
declare <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)

define <4 x i32> @test_int_x86_vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: test_int_x86_vsm3msg2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsm3msg2 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x71,0xda,0xc2]
; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
  %ret = call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
  ret <4 x i32> %ret
}
declare <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)

define <4 x i32> @test_int_x86_vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
; CHECK-LABEL: test_int_x86_vsm3rnds2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsm3rnds2 $127, %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0xde,0xc2,0x7f]
; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
  %ret = call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 127)
  ret <4 x i32> %ret
}
declare <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 %D)