# REQUIRES: riscv-registered-target
# RUN: llvm-reduce -abort-on-invalid-reduction --delta-passes=instructions -mtriple=riscv32 --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t
# RUN: FileCheck --match-full-lines %s < %t

# CHECK-INTERESTINGNESS: %{{[0-9]+}}:gpr = ADDI %{{[0-9]+}}, 5

# Verify that after reduction the following instruction sequence remains. The
# interestingness-test 'instr-reduce.py' matches a '%[0-9]+:gpr = ADDI %[0-9]+, 5'
# pattern in the output and that combined with that the MIR has to be valid
# (pass verify) results in the given sequence.

# CHECK:      [[IMPDEF:%[0-9]+]]:gpr = IMPLICIT_DEF
# CHECK-NEXT: %{{[0-9]+}}:gpr = ADDI [[IMPDEF]], 5
# CHECK-NEXT: PseudoRET implicit $x10

...
---
name:            f
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10

    %10:gpr = COPY $x10
    %20:gpr = ADDI %10, 1
    %30:gpr = ADDI %20, 5
    %40:gpr = ADDI %30, 9
    $x10 = COPY %40
    PseudoRET implicit $x10
...
---