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bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir
Sam Vervaeck 174b6f4d4e
Embed LLVM 18.1.8
2025-02-14 19:21:04 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: add
alignment: 4
legalized: true
liveins:
- { reg: '$w0' }
body: |
bb.1.entry:
liveins: $x0
; CHECK-LABEL: name: add
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 42
; CHECK-NEXT: $x0 = COPY %res(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = G_CONSTANT i64 40
%b:_(s64) = G_CONSTANT i64 2
%res:_(s64) = G_ADD %a, %b
$x0 = COPY %res(s64)
RET_ReallyLR implicit $x0
...
---
name: sub
alignment: 4
legalized: true
liveins:
- { reg: '$w0' }
body: |
bb.1.entry:
liveins: $x0
; CHECK-LABEL: name: sub
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 38
; CHECK-NEXT: $x0 = COPY %res(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = G_CONSTANT i64 40
%b:_(s64) = G_CONSTANT i64 2
%res:_(s64) = G_SUB %a, %b
$x0 = COPY %res(s64)
RET_ReallyLR implicit $x0
...
---
name: mul
alignment: 4
legalized: true
liveins:
- { reg: '$w0' }
body: |
bb.1.entry:
liveins: $x0
; CHECK-LABEL: name: mul
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 80
; CHECK-NEXT: $x0 = COPY %res(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = G_CONSTANT i64 40
%b:_(s64) = G_CONSTANT i64 2
%res:_(s64) = G_MUL %a, %b
$x0 = COPY %res(s64)
RET_ReallyLR implicit $x0
...
---
name: and
alignment: 4
legalized: true
liveins:
- { reg: '$w0' }
body: |
bb.1.entry:
liveins: $x0
; CHECK-LABEL: name: and
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: $x0 = COPY %res(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = G_CONSTANT i64 40
%b:_(s64) = G_CONSTANT i64 2
%res:_(s64) = G_AND %a, %b
$x0 = COPY %res(s64)
RET_ReallyLR implicit $x0
...
---
name: or
alignment: 4
legalized: true
liveins:
- { reg: '$w0' }
body: |
bb.1.entry:
liveins: $x0
; CHECK-LABEL: name: or
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 62
; CHECK-NEXT: $x0 = COPY %res(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = G_CONSTANT i64 42
%b:_(s64) = G_CONSTANT i64 22
%res:_(s64) = G_OR %a, %b
$x0 = COPY %res(s64)
RET_ReallyLR implicit $x0
...
---
name: xor
alignment: 4
legalized: true
liveins:
- { reg: '$w0' }
body: |
bb.1.entry:
liveins: $x0
; CHECK-LABEL: name: xor
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s64) = G_CONSTANT i64 12
; CHECK-NEXT: $x0 = COPY %res(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = G_CONSTANT i64 8
%b:_(s64) = G_CONSTANT i64 4
%res:_(s64) = G_XOR %a, %b
$x0 = COPY %res(s64)
RET_ReallyLR implicit $x0
...
---
name: fadd
legalized: true
liveins:
- { reg: '$d0' }
body: |
bb.1.entry:
liveins: $d0
; CHECK-LABEL: name: fadd
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s64) = G_FCONSTANT double 4.200000e+01
; CHECK-NEXT: $d0 = COPY %res(s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%a:_(s64) = G_FCONSTANT double 40.0
%b:_(s64) = G_FCONSTANT double 2.0
%res:_(s64) = G_FADD %a, %b
$d0 = COPY %res(s64)
RET_ReallyLR implicit $d0
...
---
name: fsub
legalized: true
liveins:
- { reg: '$d0' }
body: |
bb.1.entry:
liveins: $d0
; CHECK-LABEL: name: fsub
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s64) = G_FCONSTANT double 3.800000e+01
; CHECK-NEXT: $d0 = COPY %res(s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%a:_(s64) = G_FCONSTANT double 40.0
%b:_(s64) = G_FCONSTANT double 2.0
%res:_(s64) = G_FSUB %a, %b
$d0 = COPY %res(s64)
RET_ReallyLR implicit $d0
...
---
name: fmul
legalized: true
liveins:
- { reg: '$d0' }
body: |
bb.1.entry:
liveins: $d0
; CHECK-LABEL: name: fmul
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s64) = G_FCONSTANT double 8.000000e+01
; CHECK-NEXT: $d0 = COPY %res(s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%a:_(s64) = G_FCONSTANT double 40.0
%b:_(s64) = G_FCONSTANT double 2.0
%res:_(s64) = G_FMUL %a, %b
$d0 = COPY %res(s64)
RET_ReallyLR implicit $d0
...
---
name: fdiv
legalized: true
liveins:
- { reg: '$d0' }
body: |
bb.1.entry:
liveins: $d0
; CHECK-LABEL: name: fdiv
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s64) = G_FCONSTANT double 2.000000e+01
; CHECK-NEXT: $d0 = COPY %res(s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%a:_(s64) = G_FCONSTANT double 40.0
%b:_(s64) = G_FCONSTANT double 2.0
%res:_(s64) = G_FDIV %a, %b
$d0 = COPY %res(s64)
RET_ReallyLR implicit $d0
...
---
name: fadd32
legalized: true
liveins:
- { reg: '$s0' }
body: |
bb.1.entry:
liveins: $s0
; CHECK-LABEL: name: fadd32
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %res:_(s32) = G_FCONSTANT float 4.200000e+01
; CHECK-NEXT: $s0 = COPY %res(s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%a:_(s32) = G_FCONSTANT float 40.0
%b:_(s32) = G_FCONSTANT float 2.0
%res:_(s32) = G_FADD %a, %b
$s0 = COPY %res(s32)
RET_ReallyLR implicit $s0
...
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