160 lines
4.3 KiB
LLVM
160 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -global-isel -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32ZBB
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; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64ZBB
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declare i8 @llvm.abs.i8(i8, i1 immarg)
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declare i16 @llvm.abs.i16(i16, i1 immarg)
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declare i32 @llvm.abs.i32(i32, i1 immarg)
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declare i64 @llvm.abs.i64(i64, i1 immarg)
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define i8 @abs8(i8 %x) {
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; RV32I-LABEL: abs8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a0, 24
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; RV32I-NEXT: srai a1, a1, 24
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; RV32I-NEXT: srai a1, a1, 7
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: abs8:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: slli a0, a0, 24
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; RV32ZBB-NEXT: srai a0, a0, 24
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; RV32ZBB-NEXT: neg a1, a0
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; RV32ZBB-NEXT: max a0, a0, a1
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; RV32ZBB-NEXT: ret
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;
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; RV64I-LABEL: abs8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a0, 24
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; RV64I-NEXT: sraiw a1, a1, 24
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; RV64I-NEXT: sraiw a1, a1, 7
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: abs8:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: slli a0, a0, 56
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; RV64ZBB-NEXT: srai a0, a0, 56
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; RV64ZBB-NEXT: neg a1, a0
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; RV64ZBB-NEXT: max a0, a0, a1
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; RV64ZBB-NEXT: ret
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%abs = tail call i8 @llvm.abs.i8(i8 %x, i1 true)
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ret i8 %abs
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}
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define i16 @abs16(i16 %x) {
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; RV32I-LABEL: abs16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a0, 16
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; RV32I-NEXT: srai a1, a1, 16
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; RV32I-NEXT: srai a1, a1, 15
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: abs16:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: slli a0, a0, 16
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; RV32ZBB-NEXT: srai a0, a0, 16
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; RV32ZBB-NEXT: neg a1, a0
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; RV32ZBB-NEXT: max a0, a0, a1
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; RV32ZBB-NEXT: ret
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;
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; RV64I-LABEL: abs16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a0, 16
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; RV64I-NEXT: sraiw a1, a1, 16
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; RV64I-NEXT: sraiw a1, a1, 15
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: abs16:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: slli a0, a0, 48
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; RV64ZBB-NEXT: srai a0, a0, 48
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; RV64ZBB-NEXT: neg a1, a0
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; RV64ZBB-NEXT: max a0, a0, a1
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; RV64ZBB-NEXT: ret
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%abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
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ret i16 %abs
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}
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define i32 @abs32(i32 %x) {
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; RV32I-LABEL: abs32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: abs32:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: neg a1, a0
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; RV32ZBB-NEXT: max a0, a0, a1
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; RV32ZBB-NEXT: ret
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;
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; RV64I-LABEL: abs32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sraiw a1, a0, 31
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: abs32:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: negw a1, a0
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; RV64ZBB-NEXT: sext.w a0, a0
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; RV64ZBB-NEXT: max a0, a0, a1
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; RV64ZBB-NEXT: ret
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%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
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ret i32 %abs
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}
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define i64 @abs64(i64 %x) {
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; RV32I-LABEL: abs64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a2, a1, 31
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; RV32I-NEXT: add a0, a0, a2
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; RV32I-NEXT: sltu a3, a0, a2
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; RV32I-NEXT: add a1, a1, a2
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; RV32I-NEXT: add a1, a1, a3
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; RV32I-NEXT: xor a0, a0, a2
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; RV32I-NEXT: xor a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: abs64:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: srai a2, a1, 31
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; RV32ZBB-NEXT: add a0, a0, a2
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; RV32ZBB-NEXT: sltu a3, a0, a2
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; RV32ZBB-NEXT: add a1, a1, a2
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; RV32ZBB-NEXT: add a1, a1, a3
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; RV32ZBB-NEXT: xor a0, a0, a2
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; RV32ZBB-NEXT: xor a1, a1, a2
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; RV32ZBB-NEXT: ret
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;
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; RV64I-LABEL: abs64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srai a1, a0, 63
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: abs64:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: neg a1, a0
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; RV64ZBB-NEXT: max a0, a0, a1
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; RV64ZBB-NEXT: ret
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%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
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ret i64 %abs
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}
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