109 lines
2.7 KiB
LLVM
109 lines
2.7 KiB
LLVM
; RUN: mlir-translate -import-llvm -split-input-file %s | FileCheck %s
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; Verify the import works if the blocks are not topologically sorted.
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; CHECK-LABEL: @dominance_order
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; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]
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define i64 @dominance_order(i64 %arg1) {
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; CHECK: llvm.br ^[[BB2:.+]]
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br label %bb2
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bb1:
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; CHECK: ^[[BB1:[a-zA-Z0-9]+]]:
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; CHECK: llvm.return %[[VAL1:.+]] : i64
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ret i64 %1
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bb2:
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; CHECK: ^[[BB2]]:
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; CHECK: %[[VAL1]] = llvm.add %[[ARG1]]
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%1 = add i64 %arg1, 3
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; CHECK: llvm.br ^[[BB1]]
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br label %bb1
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}
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; // -----
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; CHECK-LABEL: @block_argument
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; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]
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; CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]
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define i64 @block_argument(i1 %arg1, i64 %arg2) {
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entry:
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; CHECK: llvm.cond_br %[[ARG1]]
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; CHECK-SAME: ^[[BB1:.+]](%[[ARG2]] : i64)
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; CHECK-SAME: ^[[BB2:.+]]
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br i1 %arg1, label %bb1, label %bb2
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bb1:
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; CHECK: ^[[BB1]](%[[BA1:.+]]: i64):
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; CHECK: llvm.return %[[BA1]] : i64
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%0 = phi i64 [ %arg2, %entry ], [ %1, %bb2 ]
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ret i64 %0
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bb2:
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; CHECK: ^[[BB2]]:
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; CHECK: %[[VAL1:.+]] = llvm.add %[[ARG2]]
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; CHECK: llvm.br ^[[BB1]](%[[VAL1]]
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%1 = add i64 %arg2, 3
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br label %bb1
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}
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; // -----
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; CHECK-LABEL: @simple_switch(
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; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]
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define i64 @simple_switch(i64 %arg1) {
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; CHECK: %[[VAL1:.+]] = llvm.add
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; CHECK: %[[VAL2:.+]] = llvm.sub
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; CHECK: %[[VAL3:.+]] = llvm.mul
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%1 = add i64 %arg1, 42
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%2 = sub i64 %arg1, 42
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%3 = mul i64 %arg1, 42
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; CHECK: llvm.switch %[[ARG1]] : i64, ^[[BBD:.+]] [
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; CHECK: 0: ^[[BB1:.+]],
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; CHECK: 9: ^[[BB2:.+]]
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; CHECK: ]
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switch i64 %arg1, label %bbd [
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i64 0, label %bb1
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i64 9, label %bb2
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]
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bb1:
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; CHECK: ^[[BB1]]:
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; CHECK: llvm.return %[[VAL1]]
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ret i64 %1
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bb2:
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; CHECK: ^[[BB2]]:
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; CHECK: llvm.return %[[VAL2]]
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ret i64 %2
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bbd:
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; CHECK: ^[[BBD]]:
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; CHECK: llvm.return %[[VAL3]]
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ret i64 %3
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}
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; // -----
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; CHECK-LABEL: @switch_args
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; CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]
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define i32 @switch_args(i32 %arg1) {
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entry:
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; CHECK: %[[VAL1:.+]] = llvm.add
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; CHECK: %[[VAL2:.+]] = llvm.sub
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; CHECK: %[[VAL3:.+]] = llvm.mul
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%0 = add i32 %arg1, 42
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%1 = sub i32 %arg1, 42
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%2 = mul i32 %arg1, 42
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; CHECK: llvm.switch %[[ARG1]] : i32, ^[[BBD:.+]](%[[VAL3]] : i32) [
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; CHECK: 0: ^[[BB1:.+]](%[[VAL1]], %[[VAL2]] : i32, i32)
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; CHECK: ]
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switch i32 %arg1, label %bbd [
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i32 0, label %bb1
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]
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bb1:
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; CHECK: ^[[BB1]](%[[BA1:.+]]: i32, %[[BA2:.+]]: i32):
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; CHECK: %[[VAL1:.*]] = llvm.add %[[BA1]], %[[BA2]] : i32
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%3 = phi i32 [%0, %entry]
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%4 = phi i32 [%1, %entry]
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%5 = add i32 %3, %4
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; CHECK: llvm.br ^[[BBD]](%[[VAL1]]
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br label %bbd
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bbd:
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; CHECK: ^[[BBD]](%[[BA3:.+]]: i32):
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; CHECK: llvm.return %[[BA3]]
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%6 = phi i32 [%2, %entry], [%5, %bb1]
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ret i32 %6
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}
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