188 lines
6.2 KiB
YAML
188 lines
6.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV64I %s
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---
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name: brcond
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; RV64I-LABEL: name: brcond
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; RV64I: bb.0:
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; RV64I-NEXT: liveins: $x10, $x11, $x12
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
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; RV64I-NEXT: [[LD:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BEQ [[LD]], [[COPY]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.1
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.1:
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; RV64I-NEXT: [[LD1:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BNE [[LD1]], [[COPY]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.2
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.2:
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; RV64I-NEXT: [[LD2:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BLT [[LD2]], [[COPY]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.3
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.3:
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; RV64I-NEXT: [[LD3:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BGE [[LD3]], [[COPY]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.4
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.4:
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; RV64I-NEXT: [[LD4:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BLTU [[LD4]], [[COPY]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.5
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.5:
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; RV64I-NEXT: [[LD5:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BGEU [[LD5]], [[COPY]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.6
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.6:
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; RV64I-NEXT: [[LD6:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BLT [[COPY]], [[LD6]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.7
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.7:
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; RV64I-NEXT: [[LD7:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BGE [[COPY]], [[LD7]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.8
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.8:
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; RV64I-NEXT: [[LD8:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BLTU [[COPY]], [[LD8]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.9
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.9:
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; RV64I-NEXT: [[LD9:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BGEU [[COPY]], [[LD9]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.10:
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; RV64I-NEXT: [[LD10:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
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; RV64I-NEXT: BNE [[ANDI]], $x0, %bb.14
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; RV64I-NEXT: PseudoBR %bb.11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.11:
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; RV64I-NEXT: successors: %bb.14(0x50000000), %bb.12(0x30000000)
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[LD11:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BGE [[LD11]], $x0, %bb.14
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; RV64I-NEXT: PseudoBR %bb.12
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.12:
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; RV64I-NEXT: successors: %bb.14(0x30000000), %bb.13(0x50000000)
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[LD12:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: BGE $x0, [[LD12]], %bb.14
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; RV64I-NEXT: PseudoBR %bb.13
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.13:
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; RV64I-NEXT: [[LD13:%[0-9]+]]:gpr = LD [[COPY1]], 0 :: (volatile load (s64))
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: bb.14:
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; RV64I-NEXT: PseudoRET
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bb.1:
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liveins: $x10, $x11, $x12
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%0:gprb(s64) = COPY $x10
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%1:gprb(p0) = COPY $x11
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%3:gprb(s64) = COPY $x12
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%26:gprb(s64) = G_CONSTANT i64 -1
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%29:gprb(s64) = G_CONSTANT i64 1
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%4:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%56:gprb(s64) = G_ICMP intpred(eq), %4(s64), %0
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G_BRCOND %56(s64), %bb.15
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G_BR %bb.2
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bb.2:
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%6:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%54:gprb(s64) = G_ICMP intpred(ne), %6(s64), %0
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G_BRCOND %54(s64), %bb.15
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G_BR %bb.3
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bb.3:
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%8:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%52:gprb(s64) = G_ICMP intpred(slt), %8(s64), %0
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G_BRCOND %52(s64), %bb.15
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G_BR %bb.4
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bb.4:
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%10:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%50:gprb(s64) = G_ICMP intpred(sge), %10(s64), %0
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G_BRCOND %50(s64), %bb.15
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G_BR %bb.5
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bb.5:
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%12:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%48:gprb(s64) = G_ICMP intpred(ult), %12(s64), %0
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G_BRCOND %48(s64), %bb.15
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G_BR %bb.6
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bb.6:
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%14:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%46:gprb(s64) = G_ICMP intpred(uge), %14(s64), %0
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G_BRCOND %46(s64), %bb.15
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G_BR %bb.7
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bb.7:
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%16:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%44:gprb(s64) = G_ICMP intpred(sgt), %16(s64), %0
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G_BRCOND %44(s64), %bb.15
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G_BR %bb.8
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bb.8:
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%18:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%42:gprb(s64) = G_ICMP intpred(sle), %18(s64), %0
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G_BRCOND %42(s64), %bb.15
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G_BR %bb.9
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bb.9:
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%20:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%40:gprb(s64) = G_ICMP intpred(ugt), %20(s64), %0
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G_BRCOND %40(s64), %bb.15
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G_BR %bb.10
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bb.10:
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%22:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%38:gprb(s64) = G_ICMP intpred(ule), %22(s64), %0
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G_BRCOND %38(s64), %bb.15
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G_BR %bb.11
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bb.11:
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%24:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%57:gprb(s64) = G_CONSTANT i64 1
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%36:gprb(s64) = G_AND %3, %57
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G_BRCOND %36(s64), %bb.15
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G_BR %bb.12
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bb.12:
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successors: %bb.15(0x50000000), %bb.13(0x30000000)
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%25:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%35:gprb(s64) = G_ICMP intpred(sgt), %25(s64), %26
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G_BRCOND %35(s64), %bb.15
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G_BR %bb.13
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bb.13:
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successors: %bb.15(0x30000000), %bb.14(0x50000000)
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%28:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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%33:gprb(s64) = G_ICMP intpred(slt), %28(s64), %29
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G_BRCOND %33(s64), %bb.15
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G_BR %bb.14
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bb.14:
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%31:gprb(s64) = G_LOAD %1(p0) :: (volatile load (s64))
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bb.15:
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PseudoRET
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...
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