34 lines
1.3 KiB
TableGen
34 lines
1.3 KiB
TableGen
//===-- RISCVInstrInfoZcmop.td -----------------------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard Compressed
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// May-Be-Operations Extension (Zcmop).
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// This version is still experimental as the 'Zcmop' extension hasn't been
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// ratified yet. It is based on v0.2 of the specification.
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//
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class CMOPInst<bits<3> imm3, string opcodestr>
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: RVInst16CI<0b011, 0b01, (outs), (ins), opcodestr, ""> {
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let Inst{6-2} = 0;
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let Inst{7} = 1;
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let Inst{10-8} = imm3;
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let Inst{12-11} = 0;
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}
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// CMOP1, CMOP5 is used by Zicfiss.
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let Predicates = [HasStdExtZcmop, NoHasStdExtZicfiss] in {
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def CMOP1 : CMOPInst<0, "cmop.1">, Sched<[]>;
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def CMOP5 : CMOPInst<2, "cmop.5">, Sched<[]>;
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}
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foreach n = [3, 7, 9, 11, 13, 15] in {
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let Predicates = [HasStdExtZcmop] in
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def CMOP # n : CMOPInst<!srl(n, 1), "cmop." # n>, Sched<[]>;
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}
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