55 lines
1.8 KiB
YAML
55 lines
1.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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# RUN: llc -run-pass=machine-scheduler %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define i32 @test_add(ptr %0) #0 {
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%2 = ptrtoint ptr %0 to i64
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%3 = and i64 %2, -64
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%4 = inttoptr i64 %3 to ptr
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%5 = load i32, ptr %4, align 64
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%6 = getelementptr inbounds i32, ptr %4, i64 1
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%7 = load i32, ptr %6, align 4
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%8 = add nsw i32 %7, %5
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ret i32 %8
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}
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attributes #0 = { "target-cpu"="ampere1" }
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...
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---
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name: test_add
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64, preferred-register: '' }
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- { id: 1, class: gpr64sp, preferred-register: '' }
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- { id: 2, class: gpr32, preferred-register: '' }
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- { id: 3, class: gpr32, preferred-register: '' }
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- { id: 4, class: gpr32, preferred-register: '' }
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liveins:
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- { reg: '$x0', virtual-reg: '%0' }
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body: |
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bb.0 (%ir-block.1):
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liveins: $x0
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; CHECK-LABEL: name: test_add
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 7865
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; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[ANDXri]], 0 :: (load (s32) from %ir.4, align 64)
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; CHECK-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[ANDXri]], 1 :: (load (s32) from %ir.6)
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; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = nsw ADDWrr [[LDRWui1]], [[LDRWui]]
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; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr64 = COPY $x0
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%1:gpr64sp = ANDXri %0, 7865
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%2:gpr32 = LDRWui %1, 0 :: (load (s32) from %ir.4, align 64)
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%3:gpr32 = LDRWui %1, 1 :: (load (s32) from %ir.6)
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%4:gpr32 = nsw ADDWrr %3, %2
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$w0 = COPY %4
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RET_ReallyLR implicit $w0
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...
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