148 lines
4.4 KiB
YAML
148 lines
4.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s
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# Make sure coalescing doesn't produce "no live segment at def" when
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# there is a live out implicit_def with subranges.
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# %1 will be coalesced into %0. %0 is a cross block implicit_def that
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# cannot be deleted. The def of %0 in %bb.2 is a live out subregister
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# def of the same register. We need to ensure that the resulting
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# subrange for %0.sub0 includes the def in %bb.1
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---
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name: liveout_implicit_def_super_reg_redefine_sub0_implicit_def
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: liveout_implicit_def_super_reg_redefine_sub0_implicit_def
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef %0.sub0:sgpr_128 = S_MOV_B32 0
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; CHECK-NEXT: S_BRANCH %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef %0.sub0:sgpr_128 = IMPLICIT_DEF
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: S_NOP 0, implicit %0
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; CHECK-NEXT: S_NOP 0, implicit %0.sub0
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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bb.1:
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%0:sgpr_128 = IMPLICIT_DEF
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%1:sgpr_32 = S_MOV_B32 0
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S_BRANCH %bb.3
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bb.2:
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undef %0.sub0:sgpr_128 = IMPLICIT_DEF
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%1:sgpr_32 = COPY %0.sub0
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bb.3:
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S_NOP 0, implicit %0
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S_NOP 0, implicit %1
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S_ENDPGM 0
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...
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# Redef of sub0 is a meaningful value.
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---
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name: liveout_implicit_def_redefine_sub0_undef_other
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: liveout_implicit_def_redefine_sub0_undef_other
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef %0.sub0:sgpr_128 = S_MOV_B32 0
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; CHECK-NEXT: S_BRANCH %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef %0.sub0:sgpr_128 = S_MOV_B32 9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: S_NOP 0, implicit %0
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; CHECK-NEXT: S_NOP 0, implicit %0.sub0
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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bb.1:
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%0:sgpr_128 = IMPLICIT_DEF
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%1:sgpr_32 = S_MOV_B32 0
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S_BRANCH %bb.3
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bb.2:
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undef %0.sub0:sgpr_128 = S_MOV_B32 9
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%1:sgpr_32 = COPY %0.sub0
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bb.3:
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S_NOP 0, implicit %0
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S_NOP 0, implicit %1
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S_ENDPGM 0
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...
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# The initial def of the register doesn't doesn't cover the redefined
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# lanes. This had no error but was useful to compare against the
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# failing cases.
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---
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name: only_redefine_undefined_lanes
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: only_redefine_undefined_lanes
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_NOP 0, implicit-def undef %0.sub1_sub2_sub3
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; CHECK-NEXT: %0.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef %0.sub0:vreg_128 = V_MOV_B32_e32 9, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: S_NOP 0, implicit %0
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; CHECK-NEXT: S_NOP 0, implicit %0.sub0
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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S_CBRANCH_SCC0 %bb.2, implicit undef $scc
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bb.1:
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S_NOP 0, implicit-def undef %0.sub1_sub2_sub3:vreg_128
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%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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S_BRANCH %bb.3
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bb.2:
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undef %0.sub0:vreg_128 = V_MOV_B32_e32 9, implicit $exec
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%1:vgpr_32 = COPY %0.sub0
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bb.3:
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S_NOP 0, implicit %0
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S_NOP 0, implicit %1
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S_ENDPGM 0
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...
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