132 lines
6.2 KiB
LLVM
132 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs -mattr=-wavefrontsize32,+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12-SDAG-W64 %s
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; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs -mattr=-wavefrontsize32,+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12-GISEL-W64 %s
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declare i32 @llvm.amdgcn.global.load.tr.i32.p1(ptr addrspace(1))
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declare <4 x i16> @llvm.amdgcn.global.load.tr.v4i16.p1(ptr addrspace(1))
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declare <4 x half> @llvm.amdgcn.global.load.tr.v4f16.p1(ptr addrspace(1))
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declare <4 x bfloat> @llvm.amdgcn.global.load.tr.v4bf16.p1(ptr addrspace(1))
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define amdgpu_kernel void @global_load_tr_b64(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
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; GFX12-SDAG-W64-LABEL: global_load_tr_b64:
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; GFX12-SDAG-W64: ; %bb.0: ; %entry
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; GFX12-SDAG-W64-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX12-SDAG-W64-NEXT: v_mov_b32_e32 v0, 0
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; GFX12-SDAG-W64-NEXT: s_wait_kmcnt 0x0
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; GFX12-SDAG-W64-NEXT: global_load_tr_b64 v1, v0, s[0:1] offset:32
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; GFX12-SDAG-W64-NEXT: s_wait_loadcnt 0x0
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; GFX12-SDAG-W64-NEXT: global_store_b32 v0, v1, s[2:3]
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; GFX12-SDAG-W64-NEXT: s_nop 0
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; GFX12-SDAG-W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-SDAG-W64-NEXT: s_endpgm
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;
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; GFX12-GISEL-W64-LABEL: global_load_tr_b64:
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; GFX12-GISEL-W64: ; %bb.0: ; %entry
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; GFX12-GISEL-W64-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX12-GISEL-W64-NEXT: v_mov_b32_e32 v0, 0
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; GFX12-GISEL-W64-NEXT: s_wait_kmcnt 0x0
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; GFX12-GISEL-W64-NEXT: global_load_tr_b64 v1, v0, s[0:1] offset:32
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; GFX12-GISEL-W64-NEXT: s_wait_loadcnt 0x0
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; GFX12-GISEL-W64-NEXT: global_store_b32 v0, v1, s[2:3]
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; GFX12-GISEL-W64-NEXT: s_nop 0
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; GFX12-GISEL-W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-GISEL-W64-NEXT: s_endpgm
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entry:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%val = call i32 @llvm.amdgcn.global.load.tr.i32.p1(ptr addrspace(1) %gep)
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store i32 %val, ptr addrspace(1) %use
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ret void
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}
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define amdgpu_kernel void @global_load_tr_b128_i16(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
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; GFX12-SDAG-W64-LABEL: global_load_tr_b128_i16:
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; GFX12-SDAG-W64: ; %bb.0: ; %entry
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; GFX12-SDAG-W64-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX12-SDAG-W64-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-SDAG-W64-NEXT: s_wait_kmcnt 0x0
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; GFX12-SDAG-W64-NEXT: global_load_tr_b128 v[0:1], v2, s[0:1] offset:32
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; GFX12-SDAG-W64-NEXT: s_wait_loadcnt 0x0
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; GFX12-SDAG-W64-NEXT: global_store_b64 v2, v[0:1], s[2:3]
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; GFX12-SDAG-W64-NEXT: s_nop 0
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; GFX12-SDAG-W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-SDAG-W64-NEXT: s_endpgm
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;
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; GFX12-GISEL-W64-LABEL: global_load_tr_b128_i16:
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; GFX12-GISEL-W64: ; %bb.0: ; %entry
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; GFX12-GISEL-W64-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX12-GISEL-W64-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-GISEL-W64-NEXT: s_wait_kmcnt 0x0
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; GFX12-GISEL-W64-NEXT: global_load_tr_b128 v[0:1], v2, s[0:1] offset:32
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; GFX12-GISEL-W64-NEXT: s_wait_loadcnt 0x0
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; GFX12-GISEL-W64-NEXT: global_store_b64 v2, v[0:1], s[2:3]
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; GFX12-GISEL-W64-NEXT: s_nop 0
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; GFX12-GISEL-W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-GISEL-W64-NEXT: s_endpgm
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entry:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%val = call <4 x i16> @llvm.amdgcn.global.load.tr.v4i16.p1(ptr addrspace(1) %gep)
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store <4 x i16> %val, ptr addrspace(1) %use
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ret void
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}
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define amdgpu_kernel void @global_load_tr_b128_half(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
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; GFX12-SDAG-W64-LABEL: global_load_tr_b128_half:
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; GFX12-SDAG-W64: ; %bb.0: ; %entry
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; GFX12-SDAG-W64-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX12-SDAG-W64-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-SDAG-W64-NEXT: s_wait_kmcnt 0x0
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; GFX12-SDAG-W64-NEXT: global_load_tr_b128 v[0:1], v2, s[0:1] offset:32
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; GFX12-SDAG-W64-NEXT: s_wait_loadcnt 0x0
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; GFX12-SDAG-W64-NEXT: global_store_b64 v2, v[0:1], s[2:3]
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; GFX12-SDAG-W64-NEXT: s_nop 0
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; GFX12-SDAG-W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-SDAG-W64-NEXT: s_endpgm
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;
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; GFX12-GISEL-W64-LABEL: global_load_tr_b128_half:
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; GFX12-GISEL-W64: ; %bb.0: ; %entry
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; GFX12-GISEL-W64-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX12-GISEL-W64-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-GISEL-W64-NEXT: s_wait_kmcnt 0x0
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; GFX12-GISEL-W64-NEXT: global_load_tr_b128 v[0:1], v2, s[0:1] offset:32
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; GFX12-GISEL-W64-NEXT: s_wait_loadcnt 0x0
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; GFX12-GISEL-W64-NEXT: global_store_b64 v2, v[0:1], s[2:3]
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; GFX12-GISEL-W64-NEXT: s_nop 0
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; GFX12-GISEL-W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-GISEL-W64-NEXT: s_endpgm
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entry:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%val = call <4 x half> @llvm.amdgcn.global.load.tr.v4f16.p1(ptr addrspace(1) %gep)
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store <4 x half> %val, ptr addrspace(1) %use
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ret void
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}
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define amdgpu_kernel void @global_load_tr_b128_bfloat(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
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; GFX12-SDAG-W64-LABEL: global_load_tr_b128_bfloat:
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; GFX12-SDAG-W64: ; %bb.0: ; %entry
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; GFX12-SDAG-W64-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX12-SDAG-W64-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-SDAG-W64-NEXT: s_wait_kmcnt 0x0
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; GFX12-SDAG-W64-NEXT: global_load_tr_b128 v[0:1], v2, s[0:1] offset:32
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; GFX12-SDAG-W64-NEXT: s_wait_loadcnt 0x0
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; GFX12-SDAG-W64-NEXT: global_store_b64 v2, v[0:1], s[2:3]
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; GFX12-SDAG-W64-NEXT: s_nop 0
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; GFX12-SDAG-W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-SDAG-W64-NEXT: s_endpgm
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;
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; GFX12-GISEL-W64-LABEL: global_load_tr_b128_bfloat:
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; GFX12-GISEL-W64: ; %bb.0: ; %entry
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; GFX12-GISEL-W64-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX12-GISEL-W64-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-GISEL-W64-NEXT: s_wait_kmcnt 0x0
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; GFX12-GISEL-W64-NEXT: global_load_tr_b128 v[0:1], v2, s[0:1] offset:32
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; GFX12-GISEL-W64-NEXT: s_wait_loadcnt 0x0
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; GFX12-GISEL-W64-NEXT: global_store_b64 v2, v[0:1], s[2:3]
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; GFX12-GISEL-W64-NEXT: s_nop 0
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; GFX12-GISEL-W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-GISEL-W64-NEXT: s_endpgm
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entry:
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%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
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%val = call <4 x bfloat> @llvm.amdgcn.global.load.tr.v4bf16.p1(ptr addrspace(1) %gep)
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store <4 x bfloat> %val, ptr addrspace(1) %use
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ret void
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}
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