163 lines
7.6 KiB
YAML
163 lines
7.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=RV64I
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# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefixes=RV64ZBB
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---
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name: smin_i8
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body: |
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bb.0.entry:
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; RV64I-LABEL: name: smin_i8
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; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
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; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
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; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
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; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
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; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
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; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
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; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ASHR]](s64), [[ASHR1]]
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; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
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; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
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; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32)
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; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
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; RV64I-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C2]](s64)
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; RV64I-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
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; RV64I-NEXT: $x10 = COPY [[ASHR2]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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;
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; RV64ZBB-LABEL: name: smin_i8
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; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
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; RV64ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
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; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
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; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
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; RV64ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
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; RV64ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
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; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASHR]], [[ASHR1]]
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; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
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; RV64ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMIN]], [[C2]](s64)
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; RV64ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
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; RV64ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
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; RV64ZBB-NEXT: PseudoRET implicit $x10
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%0:_(s64) = COPY $x10
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%1:_(s64) = COPY $x11
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%2:_(s8) = G_TRUNC %0(s64)
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%3:_(s8) = G_TRUNC %1(s64)
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%4:_(s8) = G_SMIN %2, %3
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%5:_(s64) = G_SEXT %4(s8)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: smin_i16
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body: |
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bb.0.entry:
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; RV64I-LABEL: name: smin_i16
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; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
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; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
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; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
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; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
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; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
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; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
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; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ASHR]](s64), [[ASHR1]]
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; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
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; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
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; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32)
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; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
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; RV64I-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C2]](s64)
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; RV64I-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
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; RV64I-NEXT: $x10 = COPY [[ASHR2]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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;
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; RV64ZBB-LABEL: name: smin_i16
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; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
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; RV64ZBB-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
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; RV64ZBB-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
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; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
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; RV64ZBB-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
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; RV64ZBB-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
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; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[ASHR]], [[ASHR1]]
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; RV64ZBB-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
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; RV64ZBB-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SMIN]], [[C2]](s64)
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; RV64ZBB-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[SHL2]], [[C2]](s64)
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; RV64ZBB-NEXT: $x10 = COPY [[ASHR2]](s64)
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; RV64ZBB-NEXT: PseudoRET implicit $x10
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%0:_(s64) = COPY $x10
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%1:_(s64) = COPY $x11
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%2:_(s16) = G_TRUNC %0(s64)
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%3:_(s16) = G_TRUNC %1(s64)
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%4:_(s16) = G_SMIN %2, %3
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%5:_(s64) = G_SEXT %4(s16)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: smin_i32
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body: |
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bb.0.entry:
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; RV64I-LABEL: name: smin_i32
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; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
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; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
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; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
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; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
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; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
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; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
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; RV64I-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SELECT]](s32)
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; RV64I-NEXT: $x10 = COPY [[SEXT]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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;
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; RV64ZBB-LABEL: name: smin_i32
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; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
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; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
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; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
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; RV64ZBB-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMIN]], 32
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; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG2]](s64)
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; RV64ZBB-NEXT: PseudoRET implicit $x10
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%0:_(s64) = COPY $x10
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%1:_(s64) = COPY $x11
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%2:_(s32) = G_TRUNC %0(s64)
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%3:_(s32) = G_TRUNC %1(s64)
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%4:_(s32) = G_SMIN %2, %3
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%5:_(s64) = G_SEXT %4(s32)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: smin_i64
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body: |
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bb.0.entry:
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; RV64I-LABEL: name: smin_i64
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; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64I-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
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; RV64I-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s64), [[COPY]], [[COPY1]]
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; RV64I-NEXT: $x10 = COPY [[SELECT]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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;
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; RV64ZBB-LABEL: name: smin_i64
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; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s64) = G_SMIN [[COPY]], [[COPY1]]
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; RV64ZBB-NEXT: $x10 = COPY [[SMIN]](s64)
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; RV64ZBB-NEXT: PseudoRET implicit $x10
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%0:_(s64) = COPY $x10
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%1:_(s64) = COPY $x11
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%2:_(s64) = G_SMIN %0, %1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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