555 lines
21 KiB
LLVM
555 lines
21 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX2-RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2-RV64
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; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1-RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1-RV64
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; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB
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; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVKB
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define void @bswap_v8i16(ptr %x, ptr %y) {
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; CHECK-LABEL: bswap_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vsrl.vi v9, v8, 8
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; CHECK-NEXT: vsll.vi v8, v8, 8
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; CHECK-NEXT: vor.vv v8, v8, v9
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; CHECK-NEXT: vse16.v v8, (a0)
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; CHECK-NEXT: ret
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;
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; ZVKB-LABEL: bswap_v8i16:
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; ZVKB: # %bb.0:
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; ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; ZVKB-NEXT: vle16.v v8, (a0)
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; ZVKB-NEXT: vrev8.v v8, v8
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; ZVKB-NEXT: vse16.v v8, (a0)
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; ZVKB-NEXT: ret
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%a = load <8 x i16>, ptr %x
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%b = load <8 x i16>, ptr %y
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%c = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %a)
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store <8 x i16> %c, ptr %x
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ret void
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}
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declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
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define void @bswap_v4i32(ptr %x, ptr %y) {
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; CHECK-LABEL: bswap_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vsrl.vi v9, v8, 8
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; CHECK-NEXT: lui a1, 16
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; CHECK-NEXT: addi a1, a1, -256
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; CHECK-NEXT: vand.vx v9, v9, a1
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; CHECK-NEXT: vsrl.vi v10, v8, 24
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; CHECK-NEXT: vor.vv v9, v9, v10
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; CHECK-NEXT: vand.vx v10, v8, a1
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; CHECK-NEXT: vsll.vi v10, v10, 8
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; CHECK-NEXT: vsll.vi v8, v8, 24
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; CHECK-NEXT: vor.vv v8, v8, v10
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; CHECK-NEXT: vor.vv v8, v8, v9
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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;
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; ZVKB-LABEL: bswap_v4i32:
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; ZVKB: # %bb.0:
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; ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; ZVKB-NEXT: vle32.v v8, (a0)
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; ZVKB-NEXT: vrev8.v v8, v8
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; ZVKB-NEXT: vse32.v v8, (a0)
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; ZVKB-NEXT: ret
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%a = load <4 x i32>, ptr %x
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%b = load <4 x i32>, ptr %y
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%c = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %a)
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store <4 x i32> %c, ptr %x
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ret void
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}
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declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
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define void @bswap_v2i64(ptr %x, ptr %y) {
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; RV32-LABEL: bswap_v2i64:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV32-NEXT: vle64.v v8, (a0)
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; RV32-NEXT: sw zero, 12(sp)
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; RV32-NEXT: lui a1, 1044480
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; RV32-NEXT: sw a1, 8(sp)
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; RV32-NEXT: li a1, 56
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; RV32-NEXT: vsrl.vx v9, v8, a1
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; RV32-NEXT: li a2, 40
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; RV32-NEXT: vsrl.vx v10, v8, a2
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; RV32-NEXT: lui a3, 16
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; RV32-NEXT: addi a3, a3, -256
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; RV32-NEXT: vand.vx v10, v10, a3
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; RV32-NEXT: vor.vv v9, v10, v9
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; RV32-NEXT: vsrl.vi v10, v8, 24
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; RV32-NEXT: addi a4, sp, 8
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; RV32-NEXT: vlse64.v v11, (a4), zero
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; RV32-NEXT: lui a4, 4080
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; RV32-NEXT: vand.vx v10, v10, a4
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; RV32-NEXT: vsrl.vi v12, v8, 8
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; RV32-NEXT: vand.vv v12, v12, v11
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; RV32-NEXT: vor.vv v10, v12, v10
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; RV32-NEXT: vor.vv v9, v10, v9
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; RV32-NEXT: vsll.vx v10, v8, a1
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; RV32-NEXT: vand.vx v12, v8, a3
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; RV32-NEXT: vsll.vx v12, v12, a2
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; RV32-NEXT: vor.vv v10, v10, v12
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; RV32-NEXT: vand.vx v12, v8, a4
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; RV32-NEXT: vsll.vi v12, v12, 24
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; RV32-NEXT: vand.vv v8, v8, v11
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; RV32-NEXT: vsll.vi v8, v8, 8
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; RV32-NEXT: vor.vv v8, v12, v8
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; RV32-NEXT: vor.vv v8, v10, v8
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; RV32-NEXT: vor.vv v8, v8, v9
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; RV32-NEXT: vse64.v v8, (a0)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: bswap_v2i64:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vle64.v v8, (a0)
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; RV64-NEXT: li a1, 56
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; RV64-NEXT: vsrl.vx v9, v8, a1
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; RV64-NEXT: li a2, 40
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; RV64-NEXT: vsrl.vx v10, v8, a2
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; RV64-NEXT: lui a3, 16
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; RV64-NEXT: addiw a3, a3, -256
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; RV64-NEXT: vand.vx v10, v10, a3
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; RV64-NEXT: vor.vv v9, v10, v9
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; RV64-NEXT: vsrl.vi v10, v8, 24
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; RV64-NEXT: lui a4, 4080
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; RV64-NEXT: vand.vx v10, v10, a4
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; RV64-NEXT: vsrl.vi v11, v8, 8
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; RV64-NEXT: li a5, 255
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; RV64-NEXT: slli a5, a5, 24
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; RV64-NEXT: vand.vx v11, v11, a5
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; RV64-NEXT: vor.vv v10, v11, v10
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; RV64-NEXT: vor.vv v9, v10, v9
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; RV64-NEXT: vand.vx v10, v8, a5
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; RV64-NEXT: vsll.vi v10, v10, 8
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; RV64-NEXT: vand.vx v11, v8, a4
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; RV64-NEXT: vsll.vi v11, v11, 24
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; RV64-NEXT: vor.vv v10, v11, v10
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; RV64-NEXT: vsll.vx v11, v8, a1
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; RV64-NEXT: vand.vx v8, v8, a3
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; RV64-NEXT: vsll.vx v8, v8, a2
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; RV64-NEXT: vor.vv v8, v11, v8
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; RV64-NEXT: vor.vv v8, v8, v10
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; RV64-NEXT: vor.vv v8, v8, v9
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; RV64-NEXT: vse64.v v8, (a0)
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; RV64-NEXT: ret
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;
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; ZVKB-LABEL: bswap_v2i64:
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; ZVKB: # %bb.0:
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; ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; ZVKB-NEXT: vle64.v v8, (a0)
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; ZVKB-NEXT: vrev8.v v8, v8
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; ZVKB-NEXT: vse64.v v8, (a0)
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; ZVKB-NEXT: ret
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%a = load <2 x i64>, ptr %x
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%b = load <2 x i64>, ptr %y
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%c = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a)
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store <2 x i64> %c, ptr %x
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ret void
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}
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declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
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define void @bswap_v16i16(ptr %x, ptr %y) {
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; LMULMAX2-RV32-LABEL: bswap_v16i16:
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; LMULMAX2-RV32: # %bb.0:
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; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; LMULMAX2-RV32-NEXT: vle16.v v8, (a0)
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; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8
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; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8
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; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
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; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
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; LMULMAX2-RV32-NEXT: ret
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;
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; LMULMAX2-RV64-LABEL: bswap_v16i16:
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; LMULMAX2-RV64: # %bb.0:
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; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; LMULMAX2-RV64-NEXT: vle16.v v8, (a0)
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; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8
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; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 8
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; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
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; LMULMAX2-RV64-NEXT: vse16.v v8, (a0)
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; LMULMAX2-RV64-NEXT: ret
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;
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; LMULMAX1-RV32-LABEL: bswap_v16i16:
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; LMULMAX1-RV32: # %bb.0:
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; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; LMULMAX1-RV32-NEXT: addi a1, a0, 16
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; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
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; LMULMAX1-RV32-NEXT: vle16.v v9, (a0)
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; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8
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; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 8
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; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
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; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8
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; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 8
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; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
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; LMULMAX1-RV32-NEXT: vse16.v v9, (a0)
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; LMULMAX1-RV32-NEXT: vse16.v v8, (a1)
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; LMULMAX1-RV32-NEXT: ret
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;
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; LMULMAX1-RV64-LABEL: bswap_v16i16:
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; LMULMAX1-RV64: # %bb.0:
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; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; LMULMAX1-RV64-NEXT: addi a1, a0, 16
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; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
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; LMULMAX1-RV64-NEXT: vle16.v v9, (a0)
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; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
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; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 8
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; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
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; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
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; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 8
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; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
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; LMULMAX1-RV64-NEXT: vse16.v v9, (a0)
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; LMULMAX1-RV64-NEXT: vse16.v v8, (a1)
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; LMULMAX1-RV64-NEXT: ret
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;
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; ZVKB-LABEL: bswap_v16i16:
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; ZVKB: # %bb.0:
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; ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; ZVKB-NEXT: vle16.v v8, (a0)
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; ZVKB-NEXT: vrev8.v v8, v8
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; ZVKB-NEXT: vse16.v v8, (a0)
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; ZVKB-NEXT: ret
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%a = load <16 x i16>, ptr %x
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%b = load <16 x i16>, ptr %y
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%c = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
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store <16 x i16> %c, ptr %x
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ret void
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}
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declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
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define void @bswap_v8i32(ptr %x, ptr %y) {
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; LMULMAX2-RV32-LABEL: bswap_v8i32:
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; LMULMAX2-RV32: # %bb.0:
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; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
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; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8
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; LMULMAX2-RV32-NEXT: lui a1, 16
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; LMULMAX2-RV32-NEXT: addi a1, a1, -256
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; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
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; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24
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; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12
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; LMULMAX2-RV32-NEXT: vand.vx v12, v8, a1
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; LMULMAX2-RV32-NEXT: vsll.vi v12, v12, 8
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; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24
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; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
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; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
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; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
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; LMULMAX2-RV32-NEXT: ret
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;
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; LMULMAX2-RV64-LABEL: bswap_v8i32:
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; LMULMAX2-RV64: # %bb.0:
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; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
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; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8
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; LMULMAX2-RV64-NEXT: lui a1, 16
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; LMULMAX2-RV64-NEXT: addi a1, a1, -256
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; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
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; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
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; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12
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; LMULMAX2-RV64-NEXT: vand.vx v12, v8, a1
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; LMULMAX2-RV64-NEXT: vsll.vi v12, v12, 8
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; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24
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; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
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; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
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; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
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; LMULMAX2-RV64-NEXT: ret
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;
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; LMULMAX1-RV32-LABEL: bswap_v8i32:
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; LMULMAX1-RV32: # %bb.0:
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; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; LMULMAX1-RV32-NEXT: addi a1, a0, 16
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; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
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; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
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; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8
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; LMULMAX1-RV32-NEXT: lui a2, 16
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; LMULMAX1-RV32-NEXT: addi a2, a2, -256
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; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
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; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24
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; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
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; LMULMAX1-RV32-NEXT: vand.vx v11, v8, a2
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; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
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; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
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; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
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; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
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; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8
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; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
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; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
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; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
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; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a2
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; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
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; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24
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; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
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; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
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; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
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; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
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; LMULMAX1-RV32-NEXT: ret
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;
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; LMULMAX1-RV64-LABEL: bswap_v8i32:
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; LMULMAX1-RV64: # %bb.0:
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; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; LMULMAX1-RV64-NEXT: addi a1, a0, 16
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; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
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; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
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; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
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; LMULMAX1-RV64-NEXT: lui a2, 16
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; LMULMAX1-RV64-NEXT: addi a2, a2, -256
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; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
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; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
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; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
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; LMULMAX1-RV64-NEXT: vand.vx v11, v8, a2
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; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
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; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24
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; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
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; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
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; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
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; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
|
|
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
|
|
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
|
|
; LMULMAX1-RV64-NEXT: vand.vx v11, v9, a2
|
|
; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
|
|
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24
|
|
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
|
|
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
|
|
; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
|
|
; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
|
|
; LMULMAX1-RV64-NEXT: ret
|
|
;
|
|
; ZVKB-LABEL: bswap_v8i32:
|
|
; ZVKB: # %bb.0:
|
|
; ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; ZVKB-NEXT: vle32.v v8, (a0)
|
|
; ZVKB-NEXT: vrev8.v v8, v8
|
|
; ZVKB-NEXT: vse32.v v8, (a0)
|
|
; ZVKB-NEXT: ret
|
|
%a = load <8 x i32>, ptr %x
|
|
%b = load <8 x i32>, ptr %y
|
|
%c = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %a)
|
|
store <8 x i32> %c, ptr %x
|
|
ret void
|
|
}
|
|
declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
|
|
|
|
define void @bswap_v4i64(ptr %x, ptr %y) {
|
|
; LMULMAX2-RV32-LABEL: bswap_v4i64:
|
|
; LMULMAX2-RV32: # %bb.0:
|
|
; LMULMAX2-RV32-NEXT: addi sp, sp, -16
|
|
; LMULMAX2-RV32-NEXT: .cfi_def_cfa_offset 16
|
|
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; LMULMAX2-RV32-NEXT: vle64.v v8, (a0)
|
|
; LMULMAX2-RV32-NEXT: sw zero, 12(sp)
|
|
; LMULMAX2-RV32-NEXT: lui a1, 1044480
|
|
; LMULMAX2-RV32-NEXT: sw a1, 8(sp)
|
|
; LMULMAX2-RV32-NEXT: li a1, 56
|
|
; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a1
|
|
; LMULMAX2-RV32-NEXT: li a2, 40
|
|
; LMULMAX2-RV32-NEXT: vsrl.vx v12, v8, a2
|
|
; LMULMAX2-RV32-NEXT: lui a3, 16
|
|
; LMULMAX2-RV32-NEXT: addi a3, a3, -256
|
|
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a3
|
|
; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
|
|
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24
|
|
; LMULMAX2-RV32-NEXT: addi a4, sp, 8
|
|
; LMULMAX2-RV32-NEXT: vlse64.v v14, (a4), zero
|
|
; LMULMAX2-RV32-NEXT: lui a4, 4080
|
|
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a4
|
|
; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 8
|
|
; LMULMAX2-RV32-NEXT: vand.vv v16, v16, v14
|
|
; LMULMAX2-RV32-NEXT: vor.vv v12, v16, v12
|
|
; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
|
|
; LMULMAX2-RV32-NEXT: vsll.vx v12, v8, a1
|
|
; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a3
|
|
; LMULMAX2-RV32-NEXT: vsll.vx v16, v16, a2
|
|
; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v16
|
|
; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a4
|
|
; LMULMAX2-RV32-NEXT: vsll.vi v16, v16, 24
|
|
; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v14
|
|
; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8
|
|
; LMULMAX2-RV32-NEXT: vor.vv v8, v16, v8
|
|
; LMULMAX2-RV32-NEXT: vor.vv v8, v12, v8
|
|
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
|
|
; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
|
|
; LMULMAX2-RV32-NEXT: addi sp, sp, 16
|
|
; LMULMAX2-RV32-NEXT: ret
|
|
;
|
|
; LMULMAX2-RV64-LABEL: bswap_v4i64:
|
|
; LMULMAX2-RV64: # %bb.0:
|
|
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
|
|
; LMULMAX2-RV64-NEXT: li a1, 56
|
|
; LMULMAX2-RV64-NEXT: vsrl.vx v10, v8, a1
|
|
; LMULMAX2-RV64-NEXT: li a2, 40
|
|
; LMULMAX2-RV64-NEXT: vsrl.vx v12, v8, a2
|
|
; LMULMAX2-RV64-NEXT: lui a3, 16
|
|
; LMULMAX2-RV64-NEXT: addiw a3, a3, -256
|
|
; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3
|
|
; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10
|
|
; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
|
|
; LMULMAX2-RV64-NEXT: lui a4, 4080
|
|
; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a4
|
|
; LMULMAX2-RV64-NEXT: vsrl.vi v14, v8, 8
|
|
; LMULMAX2-RV64-NEXT: li a5, 255
|
|
; LMULMAX2-RV64-NEXT: slli a5, a5, 24
|
|
; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a5
|
|
; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12
|
|
; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10
|
|
; LMULMAX2-RV64-NEXT: vand.vx v12, v8, a5
|
|
; LMULMAX2-RV64-NEXT: vsll.vi v12, v12, 8
|
|
; LMULMAX2-RV64-NEXT: vand.vx v14, v8, a4
|
|
; LMULMAX2-RV64-NEXT: vsll.vi v14, v14, 24
|
|
; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12
|
|
; LMULMAX2-RV64-NEXT: vsll.vx v14, v8, a1
|
|
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a3
|
|
; LMULMAX2-RV64-NEXT: vsll.vx v8, v8, a2
|
|
; LMULMAX2-RV64-NEXT: vor.vv v8, v14, v8
|
|
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
|
|
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
|
|
; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
|
|
; LMULMAX2-RV64-NEXT: ret
|
|
;
|
|
; LMULMAX1-RV32-LABEL: bswap_v4i64:
|
|
; LMULMAX1-RV32: # %bb.0:
|
|
; LMULMAX1-RV32-NEXT: addi sp, sp, -16
|
|
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 16
|
|
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
|
|
; LMULMAX1-RV32-NEXT: addi a1, a0, 16
|
|
; LMULMAX1-RV32-NEXT: vle64.v v9, (a1)
|
|
; LMULMAX1-RV32-NEXT: sw zero, 12(sp)
|
|
; LMULMAX1-RV32-NEXT: lui a2, 1044480
|
|
; LMULMAX1-RV32-NEXT: sw a2, 8(sp)
|
|
; LMULMAX1-RV32-NEXT: li a2, 56
|
|
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a2
|
|
; LMULMAX1-RV32-NEXT: li a3, 40
|
|
; LMULMAX1-RV32-NEXT: vsrl.vx v11, v9, a3
|
|
; LMULMAX1-RV32-NEXT: lui a4, 16
|
|
; LMULMAX1-RV32-NEXT: addi a4, a4, -256
|
|
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4
|
|
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
|
|
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
|
|
; LMULMAX1-RV32-NEXT: addi a5, sp, 8
|
|
; LMULMAX1-RV32-NEXT: vlse64.v v12, (a5), zero
|
|
; LMULMAX1-RV32-NEXT: lui a5, 4080
|
|
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a5
|
|
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v9, 8
|
|
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v12
|
|
; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11
|
|
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
|
|
; LMULMAX1-RV32-NEXT: vand.vv v11, v9, v12
|
|
; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
|
|
; LMULMAX1-RV32-NEXT: vand.vx v13, v9, a5
|
|
; LMULMAX1-RV32-NEXT: vsll.vi v13, v13, 24
|
|
; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11
|
|
; LMULMAX1-RV32-NEXT: vsll.vx v13, v9, a2
|
|
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4
|
|
; LMULMAX1-RV32-NEXT: vsll.vx v9, v9, a3
|
|
; LMULMAX1-RV32-NEXT: vor.vv v9, v13, v9
|
|
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
|
|
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
|
|
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v8, a2
|
|
; LMULMAX1-RV32-NEXT: vsrl.vx v11, v8, a3
|
|
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4
|
|
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
|
|
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24
|
|
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a5
|
|
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v8, 8
|
|
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v12
|
|
; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11
|
|
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
|
|
; LMULMAX1-RV32-NEXT: vsll.vx v11, v8, a2
|
|
; LMULMAX1-RV32-NEXT: vand.vx v13, v8, a4
|
|
; LMULMAX1-RV32-NEXT: vsll.vx v13, v13, a3
|
|
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v13
|
|
; LMULMAX1-RV32-NEXT: vand.vx v13, v8, a5
|
|
; LMULMAX1-RV32-NEXT: vsll.vi v13, v13, 24
|
|
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v12
|
|
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 8
|
|
; LMULMAX1-RV32-NEXT: vor.vv v8, v13, v8
|
|
; LMULMAX1-RV32-NEXT: vor.vv v8, v11, v8
|
|
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
|
|
; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
|
|
; LMULMAX1-RV32-NEXT: vse64.v v9, (a1)
|
|
; LMULMAX1-RV32-NEXT: addi sp, sp, 16
|
|
; LMULMAX1-RV32-NEXT: ret
|
|
;
|
|
; LMULMAX1-RV64-LABEL: bswap_v4i64:
|
|
; LMULMAX1-RV64: # %bb.0:
|
|
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; LMULMAX1-RV64-NEXT: addi a1, a0, 16
|
|
; LMULMAX1-RV64-NEXT: vle64.v v8, (a1)
|
|
; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
|
|
; LMULMAX1-RV64-NEXT: li a2, 56
|
|
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2
|
|
; LMULMAX1-RV64-NEXT: li a3, 40
|
|
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, a3
|
|
; LMULMAX1-RV64-NEXT: lui a4, 16
|
|
; LMULMAX1-RV64-NEXT: addiw a4, a4, -256
|
|
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
|
|
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
|
|
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
|
|
; LMULMAX1-RV64-NEXT: lui a5, 4080
|
|
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
|
|
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8
|
|
; LMULMAX1-RV64-NEXT: li a6, 255
|
|
; LMULMAX1-RV64-NEXT: slli a6, a6, 24
|
|
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a6
|
|
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
|
|
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
|
|
; LMULMAX1-RV64-NEXT: vand.vx v11, v8, a6
|
|
; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
|
|
; LMULMAX1-RV64-NEXT: vand.vx v12, v8, a5
|
|
; LMULMAX1-RV64-NEXT: vsll.vi v12, v12, 24
|
|
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
|
|
; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a2
|
|
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
|
|
; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a3
|
|
; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8
|
|
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
|
|
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
|
|
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2
|
|
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, a3
|
|
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
|
|
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
|
|
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
|
|
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
|
|
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8
|
|
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a6
|
|
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
|
|
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
|
|
; LMULMAX1-RV64-NEXT: vand.vx v11, v9, a6
|
|
; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
|
|
; LMULMAX1-RV64-NEXT: vand.vx v12, v9, a5
|
|
; LMULMAX1-RV64-NEXT: vsll.vi v12, v12, 24
|
|
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
|
|
; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a2
|
|
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
|
|
; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, a3
|
|
; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9
|
|
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
|
|
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
|
|
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
|
|
; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
|
|
; LMULMAX1-RV64-NEXT: ret
|
|
;
|
|
; ZVKB-LABEL: bswap_v4i64:
|
|
; ZVKB: # %bb.0:
|
|
; ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; ZVKB-NEXT: vle64.v v8, (a0)
|
|
; ZVKB-NEXT: vrev8.v v8, v8
|
|
; ZVKB-NEXT: vse64.v v8, (a0)
|
|
; ZVKB-NEXT: ret
|
|
%a = load <4 x i64>, ptr %x
|
|
%b = load <4 x i64>, ptr %y
|
|
%c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
|
|
store <4 x i64> %c, ptr %x
|
|
ret void
|
|
}
|
|
declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
|