135 lines
4.7 KiB
LLVM
135 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \
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; RUN: -verify-machineinstrs -target-abi ilp32f | \
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; RUN: FileCheck -check-prefix=RV32IZFHMIN %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \
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; RUN: -verify-machineinstrs -target-abi lp64f | \
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; RUN: FileCheck -check-prefix=RV64IZFHMIN %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
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; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d | \
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; RUN: FileCheck -check-prefix=RV32IDZFHMIN %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
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; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \
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; RUN: FileCheck -check-prefix=RV64IDZFHMIN %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinxmin \
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; RUN: -verify-machineinstrs -target-abi ilp32 | \
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; RUN: FileCheck -check-prefix=RV32IZHINXMIN %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinxmin \
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; RUN: -verify-machineinstrs -target-abi lp64 | \
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; RUN: FileCheck -check-prefix=RV64IZHINXMIN %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
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; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32 | \
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; RUN: FileCheck -check-prefix=RV32IZDINXZHINXMIN %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
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; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \
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; RUN: FileCheck -check-prefix=RV64IZDINXZHINXMIN %s
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; These intrinsics require half to be a legal type.
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declare iXLen @llvm.lrint.iXLen.f16(half)
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define iXLen @lrint_f16(half %a) nounwind {
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; RV32IZFHMIN-LABEL: lrint_f16:
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; RV32IZFHMIN: # %bb.0:
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; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5
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; RV32IZFHMIN-NEXT: ret
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;
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; RV64IZFHMIN-LABEL: lrint_f16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5
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; RV64IZFHMIN-NEXT: ret
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;
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; RV32IDZFHMIN-LABEL: lrint_f16:
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; RV32IDZFHMIN: # %bb.0:
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; RV32IDZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV32IDZFHMIN-NEXT: fcvt.w.s a0, fa5
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; RV32IDZFHMIN-NEXT: ret
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;
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; RV64IDZFHMIN-LABEL: lrint_f16:
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; RV64IDZFHMIN: # %bb.0:
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; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV64IDZFHMIN-NEXT: fcvt.l.s a0, fa5
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; RV64IDZFHMIN-NEXT: ret
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;
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; RV32IZHINXMIN-LABEL: lrint_f16:
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; RV32IZHINXMIN: # %bb.0:
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; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0
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; RV32IZHINXMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: lrint_f16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0
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; RV64IZHINXMIN-NEXT: ret
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;
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; RV32IZDINXZHINXMIN-LABEL: lrint_f16:
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; RV32IZDINXZHINXMIN: # %bb.0:
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; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0
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; RV32IZDINXZHINXMIN-NEXT: ret
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;
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; RV64IZDINXZHINXMIN-LABEL: lrint_f16:
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; RV64IZDINXZHINXMIN: # %bb.0:
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; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0
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; RV64IZDINXZHINXMIN-NEXT: ret
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%1 = call iXLen @llvm.lrint.iXLen.f16(half %a)
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ret iXLen %1
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}
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declare iXLen @llvm.lround.iXLen.f16(half)
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define iXLen @lround_f16(half %a) nounwind {
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; RV32IZFHMIN-LABEL: lround_f16:
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; RV32IZFHMIN: # %bb.0:
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; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
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; RV32IZFHMIN-NEXT: ret
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;
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; RV64IZFHMIN-LABEL: lround_f16:
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; RV64IZFHMIN: # %bb.0:
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; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rmm
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; RV64IZFHMIN-NEXT: ret
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;
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; RV32IDZFHMIN-LABEL: lround_f16:
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; RV32IDZFHMIN: # %bb.0:
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; RV32IDZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV32IDZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
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; RV32IDZFHMIN-NEXT: ret
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;
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; RV64IDZFHMIN-LABEL: lround_f16:
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; RV64IDZFHMIN: # %bb.0:
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; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; RV64IDZFHMIN-NEXT: fcvt.l.s a0, fa5, rmm
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; RV64IDZFHMIN-NEXT: ret
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;
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; RV32IZHINXMIN-LABEL: lround_f16:
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; RV32IZHINXMIN: # %bb.0:
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; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm
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; RV32IZHINXMIN-NEXT: ret
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;
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; RV64IZHINXMIN-LABEL: lround_f16:
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; RV64IZHINXMIN: # %bb.0:
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; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm
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; RV64IZHINXMIN-NEXT: ret
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;
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; RV32IZDINXZHINXMIN-LABEL: lround_f16:
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; RV32IZDINXZHINXMIN: # %bb.0:
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; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm
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; RV32IZDINXZHINXMIN-NEXT: ret
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;
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; RV64IZDINXZHINXMIN-LABEL: lround_f16:
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; RV64IZDINXZHINXMIN: # %bb.0:
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; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
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; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm
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; RV64IZDINXZHINXMIN-NEXT: ret
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%1 = call iXLen @llvm.lround.iXLen.f16(half %a)
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ret iXLen %1
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}
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