bolt/deps/llvm-18.1.8/llvm/test/MC/RISCV/rv32xtheadmac-invalid.s
2025-02-14 19:21:04 +01:00

4 lines
325 B
ArmAsm

# RUN: not llvm-mc -triple riscv32 -mattr=+xtheadmac < %s 2>&1 | FileCheck %s
th.mulaw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
th.mulsw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}