27 lines
1.5 KiB
ArmAsm
27 lines
1.5 KiB
ArmAsm
# RUN: not llvm-mc -triple riscv32 -mattr=+zdinx %s 2>&1 | FileCheck %s
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# Unsupport Odd Registers in RV32
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fadd.d a0, a1, a2 # CHECK: :[[@LINE]]:1: error: double precision floating point operands must use even numbered X register
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# Not support float registers
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flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
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fadd.d fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
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# Invalid instructions
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fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
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fmv.x.w s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
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# Invalid register names
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fadd.d a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
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fsgnjn.d a100, a2, a3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
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# Rounding mode when a register is expected
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fmadd.d x10, x12, x14, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
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# Invalid rounding modes
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fmadd.d x10, x12, x14, x16, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
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fmsub.d x10, x12, x14, x16, 0 # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
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fnmsub.d x10, x12, x14, x16, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic
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# FP registers where integer regs are expected
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fcvt.wu.d ft2, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
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